diff --git a/Changes b/Changes
index 97588814c..ab8bd168a 100644
--- a/Changes
+++ b/Changes
@@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.861 devel
 
+***   Support SV 2012 package import before port list.
+
 ****  Fix huge shifts to zero with -Wno-WIDTH, bug765. [Clifford Wolf]
 
 
diff --git a/src/verilog.y b/src/verilog.y
index 7f875c9d7..8a6c0da0e 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -727,6 +727,11 @@ package_or_generate_item_declaration<nodep>:	// ==IEEE: package_or_generate_item
 	|	';'					{ $$ = NULL; }
 	;
 
+package_import_declarationList<nodep>:
+		package_import_declaration		{ $$ = $1; }
+	|	package_import_declarationList package_import_declaration { $$ = $1->addNextNull($2); }
+	;
+
 package_import_declaration<nodep>:	// ==IEEE: package_import_declaration
 		yIMPORT package_import_itemList ';'	{ $$ = $2; }
 	;
@@ -753,7 +758,7 @@ package_import_itemObj<strp>:	// IEEE: part of package_import_item
 module_declaration:		// ==IEEE: module_declaration
 	//			// timeunits_declaration instead in module_item
 	//			// IEEE: module_nonansi_header + module_ansi_header
-		modFront parameter_port_listE portsStarE ';'
+		modFront importsAndParametersE portsStarE ';'
 			module_itemListE yENDMODULE endLabelE
 			{ $1->modTrace(v3Global.opt.trace() && $1->fileline()->tracingOn());  // Stash for implicit wires, etc
 			  if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3);
@@ -783,6 +788,12 @@ modFront<modulep>:
 			  SYMP->pushNew($$); }
 	;
 
+importsAndParametersE<nodep>:	// IEEE: common part of module_declaration, interface_declaration, program_declaration
+	//			// { package_import_declaration } [ parameter_port_list ]
+		parameter_port_listE			{ $$ = $1; }
+	|	package_import_declarationList parameter_port_listE	{ $$ = $1->addNextNull($2); }
+	;
+
 udpFront<modulep>:
 		yPRIMITIVE lifetimeE idAny
 			{ $$ = new AstPrimitive($1,*$3); $$->inLibrary(true);
diff --git a/test_regress/t/t_package_twodeep.v b/test_regress/t/t_package_twodeep.v
index c8c8ed4a3..3008e1cfd 100644
--- a/test_regress/t/t_package_twodeep.v
+++ b/test_regress/t/t_package_twodeep.v
@@ -14,14 +14,14 @@ package pkg1;
    parameter PARAM1 = 8;
 endpackage // pkg1
 
-module t (/*AUTOARG*/
+module t
+  import pkg1::*;   // Test SV 2012 import format
+  (/*AUTOARG*/
    // Inputs
    clk
    );
    input clk;
 
-   import pkg1::*;
-
    reg [PARAM1:0] bus1;
 
    initial begin