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Add FSM arc coverage to verilator_coverage .info output 

Signed-off-by: Igor Zaworski <izaworski@antmicro.com>
This commit is contained in:
Igor Zaworski 2026-07-22 18:26:14 +02:00 committed by GitHub
parent 0a855fce47
commit f511f6c34d
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GPG Key ID: B5690EEEBB952194
3 changed files with 39 additions and 3 deletions
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9
src/VlcTop.cpp
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@ -262,7 +262,6 @@ void VlcTop::writeInfo(const string& filename) {
uint64_t daCount = 0; uint64_t daCount = 0;
std::vector<const VlcPoint*> infoPoints; std::vector<const VlcPoint*> infoPoints;
for (const auto& point : sc.points()) { for (const auto& point : sc.points()) {
if (point->isFsmArc()) continue;
daCount = std::max(daCount, point->count()); daCount = std::max(daCount, point->count());
infoPoints.push_back(point); infoPoints.push_back(point);
} }
@ -272,10 +271,14 @@ void VlcTop::writeInfo(const string& filename) {
int point_num = 0; int point_num = 0;
for (const VlcPoint* point : infoPoints) { for (const VlcPoint* point : infoPoints) {
os << "BRDA:" << sc.lineno() << ","; os << "BRDA:" << sc.lineno() << ",";
os << "0,"; if (point->isFsmArc()) {
if (point->comment().empty()) { os << "2,";
os << point->fsmFromState() << "->" << point->fsmToState();
} else if (point->comment().empty()) {
os << "0,";
os << point_num; os << point_num;
} else { } else {
os << (point->isFsmState() ? '1' : '0') << ',';
std::string comment(point->comment()); std::string comment(point->comment());
std::replace(comment.begin(), comment.end(), ',', '_'); std::replace(comment.begin(), comment.end(), ',', '_');
os << comment; os << comment;

11
test_regress/t/t_vlcov_opt_fsm_arc.info.out Normal file
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@ -0,0 +1,11 @@
TN:verilator_coverage
SF:t/t_cover_fsm_basic.v
DA:45,4
BRDA:45,2,ANY->S_IDLE,1
BRDA:45,2,S_DONE->S_DONE,4
BRDA:45,2,S_IDLE->S_IDLE,3
BRDA:45,2,S_IDLE->S_RUN,1
BRDA:45,2,S_RUN->S_DONE,1
BRF:5
BRH:0
end_of_record

22
test_regress/t/t_vlcov_opt_fsm_arc.py Executable file
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@ -0,0 +1,22 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('dist')
test.run(cmd=[
os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info",
test.obj_dir + "/coverage.info", "--filter-type fsm_arc", "t/t_vlcov_data_g.dat"
],
verilator_run=True)
test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out")
test.passes()