Fix to be in verilog 2005, bug1319.

Signed-off-by: Wilson Snyder <[email protected]>

Changes

@@ -14,6 +14,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix parsing error on bad missing #, bug1308. [Dan Kirkham]
 
+****  Fix $clog2 to be in verilog 2005, bug1319. [James Hutchinson]
+
 
 * Verilator 3.922 2018-03-17
 

src/verilog.l

@@ -422,6 +422,8 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 
   /* Verilog 2005 */
 <V05,S05,S09,S12,S17,SAX>{
+  /*     System Tasks */
+  "$clog2"		{ FL; return yD_CLOG2; }
   /*     Keywords */
   "uwire"		{ FL; return yWIRE; }
 }
@@ -430,7 +432,6 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 <S05,S09,S12,S17,SAX>{
   /*     System Tasks */
   "$bits"		{ FL; return yD_BITS; }
-  "$clog2"		{ FL; return yD_CLOG2; }
   "$countones"		{ FL; return yD_COUNTONES; }
   "$dimensions"		{ FL; return yD_DIMENSIONS; }
   "$error"		{ FL; return yD_ERROR; }