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Tests: Add t_tri_array and enable t_sv_cpu.

This commit is contained in:
Wilson Snyder 2014-06-10 20:02:18 -04:00
parent e26ab67e25
commit eed3c5e543
7 changed files with 120 additions and 8 deletions
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4
test_regress/t/t_sv_cpu.pl
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@ -10,8 +10,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett,
# Embecosm.
$Self->{vlt} and $Self->unsupported("Verilator unsupported");
compile (
# Taken from the original VCS command line.
v_flags2 => ["t/t_sv_cpu_code/timescale.sv",
@ -33,7 +31,7 @@ compile (
"t/t_sv_cpu_code/cpu.sv",
"t/t_sv_cpu_code/chip.sv"],
vcs_flags2 => ["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"],
verilator_flags2 => ["-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"],
verilator_flags2 => ["-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t"],
iv_flags2 => ["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"],
);

8
test_regress/t/t_sv_cpu.v
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@ -63,7 +63,7 @@ module t (/*AUTOARG*/
end
always @( posedge clk ) begin
if (500 == clk_count) begin
if (90 == clk_count) begin
$finish ();
end
else begin
@ -103,7 +103,11 @@ module testbench (/*AUTOARG*/
// **************************************************************************
// **** Pinout ****
`ifdef VERILATOR // see t_tri_array
wire [NUMPADS:1] pad; // GPIO Pads (PORT{A,...,R}).
`else
wire pad [1:NUMPADS]; // GPIO Pads (PORT{A,...,R}).
`endif
// **************************************************************************
@ -129,7 +133,7 @@ module testbench (/*AUTOARG*/
(
/*AUTOINST*/
// Inouts
.pad (pad),
.pad (pad[NUMPADS:1]),
// Inputs
.clk (clk),
.rst (rst));

4
test_regress/t/t_sv_cpu_code/chip.sv
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@ -15,7 +15,11 @@ module chip
)
(
// **** Pinout ****
`ifdef VERILATOR // see t_tri_array
inout wire [NUMPADS:1] pad,
`else
inout wire pad [1:NUMPADS],
`endif
// **** Inputs !!!! ****
input logic clk,

2
test_regress/t/t_sv_cpu_code/pad_gpio.sv
View File

@ -26,7 +26,9 @@ module pad_gpio
);
// **** Analog <-> pad connection ****
`ifndef VERILATOR //TODO alias
alias ana = pad;
`endif
// **** Digital driver <-> pad connection ****

20
test_regress/t/t_sv_cpu_code/pads.sv
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@ -19,8 +19,11 @@ module pads
// **** Pinout ****
`ifdef VERILATOR // see t_tri_array
inout wire [NUMPADS:1] pad,
`else
inout wire pad [1:NUMPADS],
`endif
// **** Inputs ****
input logic clk,
@ -32,6 +35,11 @@ module pads
// Code Section
// ***************************************************************************
`ifdef VERILATOR // see t_tri_array
tri [NUMPADS:1] _anahack;
`endif
genvar i;
for ( i = 1; i <= NUMPADS; i++ )
begin
@ -46,11 +54,16 @@ module pads
case ( p_type )
PADTYPE_GPIO:
pad_gpio #( .ID( i ) )
i_pad_gpio(.pad (pad [i]),
i_pad_gpio(
.pad (pad [i]),
// Outputs
.input_val (padsif.input_val [i]),
// Inouts
`ifdef VERILATOR // see t_tri_array
.ana (_anahack [i]),
`else
.ana (padsif.ana [i]),
`endif
// Inputs
.pullup_en (padsif.pullup_en [i]),
.pulldown_en (padsif.pulldown_en [i]),
@ -63,7 +76,8 @@ module pads
PADTYPE_VDD:
begin
pad_vdd #( .ID( i ) )
i_pad_vdd(.pad (pad[i])
i_pad_vdd(
.pad (pad[i])
/*AUTOINST*/);
// Not SV standard, yet... assign padsif.input_val[i] = ();
end

21
test_regress/t/t_tri_array.pl Executable file
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@ -0,0 +1,21 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# When fix, update ifdefs in t_sv_cpu files; search for t_tri_array
$Self->{vlt} and $Self->unsupported("Verilator unsupported, tristate arrays");
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

69
test_regress/t/t_tri_array.v Normal file
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@ -0,0 +1,69 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
parameter NPAD = 4;
tri pad [NPAD-1:0]; // Array
wire [NPAD-1:0] data0 = crc[0 +: 4];
wire [NPAD-1:0] data1 = crc[8 +: 4];
wire [NPAD-1:0] en = crc[16 +: 4];
for (genvar g=0; g<NPAD; ++g) begin : gpad
Pad pad1 (.pad(pad[g]),
.ena(en[g]),
.data(data1[g]));
Pad pad0 (.pad(pad[g]),
.ena(!en[g]),
.data(data0[g]));
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {60'h0, pad[3], pad[2], pad[1], pad[0]}
^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'he09fe6f2dfd7a302
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Pad
(inout pad,
input ena,
input data);
assign pad = ena ? data : 1'bz;
endmodule