diff --git a/test_regress/t/t_sv_cpu.pl b/test_regress/t/t_sv_cpu.pl index e9167a0b2..2d864dc4a 100755 --- a/test_regress/t/t_sv_cpu.pl +++ b/test_regress/t/t_sv_cpu.pl @@ -10,8 +10,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett, # Embecosm. -$Self->{vlt} and $Self->unsupported("Verilator unsupported"); - compile ( # Taken from the original VCS command line. v_flags2 => ["t/t_sv_cpu_code/timescale.sv", @@ -33,7 +31,7 @@ compile ( "t/t_sv_cpu_code/cpu.sv", "t/t_sv_cpu_code/chip.sv"], vcs_flags2 => ["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"], - verilator_flags2 => ["-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"], + verilator_flags2 => ["-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t"], iv_flags2 => ["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"], ); diff --git a/test_regress/t/t_sv_cpu.v b/test_regress/t/t_sv_cpu.v index fb08d0d6d..efa0449c3 100644 --- a/test_regress/t/t_sv_cpu.v +++ b/test_regress/t/t_sv_cpu.v @@ -63,7 +63,7 @@ module t (/*AUTOARG*/ end always @( posedge clk ) begin - if (500 == clk_count) begin + if (90 == clk_count) begin $finish (); end else begin @@ -103,7 +103,11 @@ module testbench (/*AUTOARG*/ // ************************************************************************** // **** Pinout **** +`ifdef VERILATOR // see t_tri_array + wire [NUMPADS:1] pad; // GPIO Pads (PORT{A,...,R}). +`else wire pad [1:NUMPADS]; // GPIO Pads (PORT{A,...,R}). +`endif // ************************************************************************** @@ -129,7 +133,7 @@ module testbench (/*AUTOARG*/ ( /*AUTOINST*/ // Inouts - .pad (pad), + .pad (pad[NUMPADS:1]), // Inputs .clk (clk), .rst (rst)); diff --git a/test_regress/t/t_sv_cpu_code/chip.sv b/test_regress/t/t_sv_cpu_code/chip.sv index 276b2a8cc..50a5da6bb 100644 --- a/test_regress/t/t_sv_cpu_code/chip.sv +++ b/test_regress/t/t_sv_cpu_code/chip.sv @@ -15,7 +15,11 @@ module chip ) ( // **** Pinout **** +`ifdef VERILATOR // see t_tri_array + inout wire [NUMPADS:1] pad, +`else inout wire pad [1:NUMPADS], +`endif // **** Inputs !!!! **** input logic clk, diff --git a/test_regress/t/t_sv_cpu_code/pad_gpio.sv b/test_regress/t/t_sv_cpu_code/pad_gpio.sv index 841379ec6..18763de51 100644 --- a/test_regress/t/t_sv_cpu_code/pad_gpio.sv +++ b/test_regress/t/t_sv_cpu_code/pad_gpio.sv @@ -26,7 +26,9 @@ module pad_gpio ); // **** Analog <-> pad connection **** +`ifndef VERILATOR //TODO alias alias ana = pad; +`endif // **** Digital driver <-> pad connection **** diff --git a/test_regress/t/t_sv_cpu_code/pads.sv b/test_regress/t/t_sv_cpu_code/pads.sv index aec8dfafa..d8ac363d1 100644 --- a/test_regress/t/t_sv_cpu_code/pads.sv +++ b/test_regress/t/t_sv_cpu_code/pads.sv @@ -19,8 +19,11 @@ module pads // **** Pinout **** +`ifdef VERILATOR // see t_tri_array + inout wire [NUMPADS:1] pad, +`else inout wire pad [1:NUMPADS], - +`endif // **** Inputs **** input logic clk, @@ -32,6 +35,11 @@ module pads // Code Section // *************************************************************************** +`ifdef VERILATOR // see t_tri_array + tri [NUMPADS:1] _anahack; +`endif + + genvar i; for ( i = 1; i <= NUMPADS; i++ ) begin @@ -46,11 +54,16 @@ module pads case ( p_type ) PADTYPE_GPIO: pad_gpio #( .ID( i ) ) - i_pad_gpio(.pad (pad [i]), + i_pad_gpio( + .pad (pad [i]), // Outputs .input_val (padsif.input_val [i]), // Inouts +`ifdef VERILATOR // see t_tri_array + .ana (_anahack [i]), +`else .ana (padsif.ana [i]), +`endif // Inputs .pullup_en (padsif.pullup_en [i]), .pulldown_en (padsif.pulldown_en [i]), @@ -63,7 +76,8 @@ module pads PADTYPE_VDD: begin pad_vdd #( .ID( i ) ) - i_pad_vdd(.pad (pad[i]) + i_pad_vdd( + .pad (pad[i]) /*AUTOINST*/); // Not SV standard, yet... assign padsif.input_val[i] = (); end diff --git a/test_regress/t/t_tri_array.pl b/test_regress/t/t_tri_array.pl new file mode 100755 index 000000000..cc522f7b4 --- /dev/null +++ b/test_regress/t/t_tri_array.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +# When fix, update ifdefs in t_sv_cpu files; search for t_tri_array +$Self->{vlt} and $Self->unsupported("Verilator unsupported, tristate arrays"); + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_tri_array.v b/test_regress/t/t_tri_array.v new file mode 100644 index 000000000..a110a3780 --- /dev/null +++ b/test_regress/t/t_tri_array.v @@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + parameter NPAD = 4; + + tri pad [NPAD-1:0]; // Array + wire [NPAD-1:0] data0 = crc[0 +: 4]; + wire [NPAD-1:0] data1 = crc[8 +: 4]; + wire [NPAD-1:0] en = crc[16 +: 4]; + + for (genvar g=0; g