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Allow assigns to create implicit wires

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@1004 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder
2008-03-20 01:40:22 +00:00
parent 4a1729eaab
commit ede37bb9d8
5 changed files with 62 additions and 4 deletions
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src/V3Link.cpp
+4 -4
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@@ -381,10 +381,10 @@ private:
virtual void visit(AstAssignW* nodep, AstNUser*) {
// Deal with implicit definitions
if (nodep->allowImplicit()) {
if (AstVarRef* forrefp = nodep->lhsp()->castVarRef()) {
createImplicitVar(forrefp, false);
}
// We used to nodep->allowImplicit() here, but it turns out
// normal "assigns" can also make implicit wires. Yuk.
if (AstVarRef* forrefp = nodep->lhsp()->castVarRef()) {
createImplicitVar(forrefp, false);
}
nodep->iterateChildren(*this);
}