diff --git a/Changes b/Changes
index e10aaa4db..f8ebc5b4f 100644
--- a/Changes
+++ b/Changes
@@ -22,6 +22,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix definitions in main file.v, referenced in library.  [Stefan Thiede]
 
+**** Fix undefined assigns to be implicit warnings. [Stefan Thiede]
+
 * Verilator 3.658 2008/02/25
 
 **** Fix unistd compile error in 3.657.  [Patricio Kaplan, Jonathan Kimmitt]
diff --git a/src/V3Link.cpp b/src/V3Link.cpp
index ec1ecb66e..828a58463 100644
--- a/src/V3Link.cpp
+++ b/src/V3Link.cpp
@@ -381,10 +381,10 @@ private:
 
     virtual void visit(AstAssignW* nodep, AstNUser*) {
 	// Deal with implicit definitions
-	if (nodep->allowImplicit()) {
-	    if (AstVarRef* forrefp = nodep->lhsp()->castVarRef()) {
-		createImplicitVar(forrefp, false);
-	    }
+	// We used to nodep->allowImplicit() here, but it turns out
+	// normal "assigns" can also make implicit wires.  Yuk.
+	if (AstVarRef* forrefp = nodep->lhsp()->castVarRef()) {
+	    createImplicitVar(forrefp, false);
 	}
 	nodep->iterateChildren(*this);
     }
diff --git a/test_regress/t/t_lint_implicit.pl b/test_regress/t/t_lint_implicit.pl
new file mode 100755
index 000000000..91837914b
--- /dev/null
+++ b/test_regress/t/t_lint_implicit.pl
@@ -0,0 +1,16 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => ["-Wno-IMPLICIT"],
+	 ) if $Last_Self->{v3};
+
+ok(1);
+1;
+
diff --git a/test_regress/t/t_lint_implicit.v b/test_regress/t/t_lint_implicit.v
new file mode 100644
index 000000000..3a8e3b24c
--- /dev/null
+++ b/test_regress/t/t_lint_implicit.v
@@ -0,0 +1,16 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module t (a,z);
+   input a;
+   output z;
+
+   assign b = 1'b1;
+
+   or   OR0 (nt0, a, b);
+
+   assign z = nt0;
+endmodule
diff --git a/test_regress/t/t_lint_implicit_bad.pl b/test_regress/t/t_lint_implicit_bad.pl
new file mode 100755
index 000000000..17686cb53
--- /dev/null
+++ b/test_regress/t/t_lint_implicit_bad.pl
@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_lint_implicit.v");
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+'%Warning-IMPLICIT: t/t_lint_implicit.v:\d+: Signal definition not found, creating implicitly: b
+%Warning-IMPLICIT: Use .* to disable this message.
+%Warning-IMPLICIT: t/t_lint_implicit.v:\d+: Signal definition not found, creating implicitly: nt0
+%Error: Exiting due to.*',
+	 ) if $Last_Self->{v3};
+
+ok(1);
+1;
+