[#72179] add t_trace_abort test for SAIF

test_regress/t/t_trace_abort.saif

@@ -0,0 +1,15 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "foo")
+(PROGRAM_NAME "Verilator")
+(VERSION "5.032")
+(DIVIDER .)
+(TIMESCALE 1ps)
+(DURATION 75)
+(INSTANCE foo (NET
+(cyc[0] (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 7))
+(cyc[1] (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 3))
+(cyc[2] (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 1))
+(clk (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 14))
+)))

test_regress/t/t_trace_abort_saif.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t/t_trace_abort.v"
+
+test.compile(verilator_flags2=['--cc --trace'])
+
+test.execute(fails=True)
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()