luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

[#72179] add saif_example design files

This commit is contained in:
Mateusz Gancarz 2025-02-13 14:20:40 +01:00
parent de7d9e37c5
commit 8b3ebddeff
7 changed files with 632 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

92
examples/saif_example/saif_trace_example/autotuner.json Normal file
View File

@ -0,0 +1,92 @@
{
"_SDC_FILE_PATH": "constraint.sdc",
"_SDC_CLK_PERIOD": {
"type": "float",
"minmax": [
1200,
2000
],
"step": 0
},
"CORE_UTILIZATION": {
"type": "int",
"minmax": [
5,
10
],
"step": 1
},
"CORE_ASPECT_RATIO": {
"type": "float",
"minmax": [
0.9,
1.1
],
"step": 0
},
"CORE_MARGIN": {
"type": "int",
"minmax": [
2,
2
],
"step": 0
},
"CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
"type": "int",
"minmax": [
0,
3
],
"step": 1
},
"CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
"type": "int",
"minmax": [
0,
3
],
"step": 1
},
"_FR_LAYER_ADJUST": {
"type": "float",
"minmax": [
0.0,
0.1
],
"step": 0
},
"PLACE_DENSITY_LB_ADDON": {
"type": "float",
"minmax": [
0.0,
0.2
],
"step": 0
},
"_PINS_DISTANCE": {
"type": "int",
"minmax": [
1,
1
],
"step": 1
},
"CTS_CLUSTER_SIZE": {
"type": "int",
"minmax": [
10,
200
],
"step": 1
},
"CTS_CLUSTER_DIAMETER": {
"type": "int",
"minmax": [
20,
400
],
"step": 1
},
"_FR_FILE_PATH": ""
}

17
examples/saif_example/saif_trace_example/config.mk Normal file
View File

@ -0,0 +1,17 @@
export PLATFORM = asap7
export DESIGN_NICKNAME = saif_trace_example
export DESIGN_NAME = t
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export CORE_UTILIZATION = 40
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN = 2
export PLACE_DENSITY_LB_ADDON = 0.20
export ENABLE_DPO = 0
export TNS_END_PERCENT = 100

13
examples/saif_example/saif_trace_example/constraint.sdc Normal file
View File

@ -0,0 +1,13 @@
set clk_name core_clock
set clk_port_name clk
set clk_period 1260
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

384
examples/saif_example/saif_trace_example/metadata-base-ok.json Normal file
View File

@ -0,0 +1,384 @@
{
"constraints__clocks__count": 1,
"constraints__clocks__details": [
"core_clock: 1260.0000"
],
"cts__clock__skew__hold": 128.848,
"cts__clock__skew__setup": 154.028,
"cts__cpu__total": 90.71,
"cts__design__core__area": 5654.27,
"cts__design__die__area": 6307.06,
"cts__design__instance__area": 2632.36,
"cts__design__instance__area__cover": 0,
"cts__design__instance__area__macros": 0,
"cts__design__instance__area__padcells": 0,
"cts__design__instance__area__stdcell": 2632.36,
"cts__design__instance__count": 21501,
"cts__design__instance__count__cover": 0,
"cts__design__instance__count__hold_buffer": 0,
"cts__design__instance__count__macros": 0,
"cts__design__instance__count__padcells": 0,
"cts__design__instance__count__setup_buffer": 62,
"cts__design__instance__count__stdcell": 21501,
"cts__design__instance__displacement__max": 1.116,
"cts__design__instance__displacement__mean": 0.001,
"cts__design__instance__displacement__total": 39.259,
"cts__design__instance__utilization": 0.465553,
"cts__design__instance__utilization__stdcell": 0.465553,
"cts__design__io": 264,
"cts__design__rows": 278,
"cts__design__rows:asap7sc7p5t": 278,
"cts__design__sites": 387810,
"cts__design__sites:asap7sc7p5t": 387810,
"cts__design__violations": 0,
"cts__flow__errors__count": 0,
"cts__flow__warnings__count": 11,
"cts__mem__peak": 723160.0,
"cts__power__internal__total": 0.0206542,
"cts__power__leakage__total": 2.02506e-06,
"cts__power__switching__total": 0.0215231,
"cts__power__total": 0.0421793,
"cts__route__wirelength__estimated": 94069.5,
"cts__runtime__total": "1:31.32",
"cts__timing__drv__hold_violation_count": 0,
"cts__timing__drv__max_cap": 0,
"cts__timing__drv__max_cap_limit": 0.424876,
"cts__timing__drv__max_fanout": 0,
"cts__timing__drv__max_fanout_limit": 0,
"cts__timing__drv__max_slew": 0,
"cts__timing__drv__max_slew_limit": 0.219039,
"cts__timing__drv__setup_violation_count": 3,
"cts__timing__setup__tns": -38.9303,
"cts__timing__setup__ws": -32.5814,
"design__io__hpwl": 5296159,
"design__violations": 0,
"detailedplace__cpu__total": 135.62,
"detailedplace__design__core__area": 5654.27,
"detailedplace__design__die__area": 6307.06,
"detailedplace__design__instance__area": 2564.9,
"detailedplace__design__instance__area__cover": 0,
"detailedplace__design__instance__area__macros": 0,
"detailedplace__design__instance__area__padcells": 0,
"detailedplace__design__instance__area__stdcell": 2564.9,
"detailedplace__design__instance__count": 21241,
"detailedplace__design__instance__count__cover": 0,
"detailedplace__design__instance__count__macros": 0,
"detailedplace__design__instance__count__padcells": 0,
"detailedplace__design__instance__count__stdcell": 21241,
"detailedplace__design__instance__displacement__max": 2.088,
"detailedplace__design__instance__displacement__mean": 0.215,
"detailedplace__design__instance__displacement__total": 4584.86,
"detailedplace__design__instance__utilization": 0.453622,
"detailedplace__design__instance__utilization__stdcell": 0.453622,
"detailedplace__design__io": 264,
"detailedplace__design__rows": 278,
"detailedplace__design__rows:asap7sc7p5t": 278,
"detailedplace__design__sites": 387810,
"detailedplace__design__sites:asap7sc7p5t": 387810,
"detailedplace__design__violations": 0,
"detailedplace__flow__errors__count": 0,
"detailedplace__flow__warnings__count": 10,
"detailedplace__mem__peak": 860888.0,
"detailedplace__power__internal__total": 0.0186292,
"detailedplace__power__leakage__total": 1.96045e-06,
"detailedplace__power__switching__total": 0.0203954,
"detailedplace__power__total": 0.0390265,
"detailedplace__route__wirelength__estimated": 92018.4,
"detailedplace__runtime__total": "2:16.23",
"detailedplace__timing__drv__hold_violation_count": 0,
"detailedplace__timing__drv__max_cap": 0,
"detailedplace__timing__drv__max_cap_limit": 0.42514,
"detailedplace__timing__drv__max_fanout": 0,
"detailedplace__timing__drv__max_fanout_limit": 0,
"detailedplace__timing__drv__max_slew": 0,
"detailedplace__timing__drv__max_slew_limit": 0.0523232,
"detailedplace__timing__drv__setup_violation_count": 255,
"detailedplace__timing__setup__tns": -25892.2,
"detailedplace__timing__setup__ws": -168.407,
"detailedroute__antenna__violating__nets": 0,
"detailedroute__antenna__violating__pins": 0,
"detailedroute__antenna_diodes_count": 0,
"detailedroute__flow__errors__count": 0,
"detailedroute__flow__warnings__count": 11,
"detailedroute__route__drc_errors": 0,
"detailedroute__route__drc_errors__iter:0": 5192,
"detailedroute__route__drc_errors__iter:1": 553,
"detailedroute__route__drc_errors__iter:2": 372,
"detailedroute__route__drc_errors__iter:3": 7,
"detailedroute__route__drc_errors__iter:4": 0,
"detailedroute__route__net": 21209,
"detailedroute__route__net__special": 2,
"detailedroute__route__vias": 214163,
"detailedroute__route__vias__multicut": 0,
"detailedroute__route__vias__singlecut": 214163,
"detailedroute__route__wirelength": 115245,
"detailedroute__route__wirelength__iter:0": 116008,
"detailedroute__route__wirelength__iter:1": 115332,
"detailedroute__route__wirelength__iter:2": 115236,
"detailedroute__route__wirelength__iter:3": 115244,
"detailedroute__route__wirelength__iter:4": 115245,
"finish__clock__skew__hold": 137.921,
"finish__clock__skew__setup": 164.227,
"finish__cpu__total": 145.58,
"finish__design__core__area": 5654.27,
"finish__design__die__area": 6307.06,
"finish__design__instance__area": 2639.14,
"finish__design__instance__area__class:buffer": 234.067,
"finish__design__instance__area__class:clock_buffer": 52.765,
"finish__design__instance__area__class:clock_inverter": 9.27288,
"finish__design__instance__area__class:inverter": 81.4147,
"finish__design__instance__area__class:multi_input_combinational_cell": 1410.28,
"finish__design__instance__area__class:sequential_cell": 712.481,
"finish__design__instance__area__class:tie_cell": 72.7834,
"finish__design__instance__area__class:timing_repair_buffer": 37.4998,
"finish__design__instance__area__class:timing_repair_inverter": 0.11664,
"finish__design__instance__area__cover": 0,
"finish__design__instance__area__macros": 0,
"finish__design__instance__area__padcells": 0,
"finish__design__instance__area__stdcell": 2639.14,
"finish__design__instance__count": 21541,
"finish__design__instance__count__class:buffer": 1708,
"finish__design__instance__count__class:clock_buffer": 140,
"finish__design__instance__count__class:clock_inverter": 55,
"finish__design__instance__count__class:inverter": 1689,
"finish__design__instance__count__class:multi_input_combinational_cell": 12991,
"finish__design__instance__count__class:sequential_cell": 1932,
"finish__design__instance__count__class:tie_cell": 1664,
"finish__design__instance__count__class:timing_repair_buffer": 384,
"finish__design__instance__count__class:timing_repair_inverter": 2,
"finish__design__instance__count__cover": 0,
"finish__design__instance__count__macros": 0,
"finish__design__instance__count__padcells": 0,
"finish__design__instance__count__stdcell": 21541,
"finish__design__instance__utilization": 0.466752,
"finish__design__instance__utilization__stdcell": 0.466752,
"finish__design__io": 264,
"finish__design__rows": 278,
"finish__design__rows:asap7sc7p5t": 278,
"finish__design__sites": 387810,
"finish__design__sites:asap7sc7p5t": 387810,
"finish__design_powergrid__drop__average__net:VDD__corner:default": 0.7501,
"finish__design_powergrid__drop__average__net:VSS__corner:default": 0.0194608,
"finish__design_powergrid__drop__worst__net:VDD__corner:default": 0.052146,
"finish__design_powergrid__drop__worst__net:VSS__corner:default": 0.0505833,
"finish__design_powergrid__voltage__worst__net:VDD__corner:default": 0.717854,
"finish__design_powergrid__voltage__worst__net:VSS__corner:default": 0.0505833,
"finish__flow__errors__count": 0,
"finish__flow__warnings__count": 10,
"finish__mem__peak": 875068.0,
"finish__power__internal__total": 0.0205475,
"finish__power__leakage__total": 2.03126e-06,
"finish__power__switching__total": 0.0227261,
"finish__power__total": 0.0432756,
"finish__runtime__total": "2:26.72",
"finish__timing__drv__hold_violation_count": 0,
"finish__timing__drv__max_cap": 0,
"finish__timing__drv__max_cap_limit": 0.356024,
"finish__timing__drv__max_fanout": 0,
"finish__timing__drv__max_fanout_limit": 0,
"finish__timing__drv__max_slew": 45,
"finish__timing__drv__max_slew_limit": -0.331023,
"finish__timing__drv__setup_violation_count": 100,
"finish__timing__setup__tns": -2214.04,
"finish__timing__setup__ws": -64.3049,
"finish__timing__wns_percent_delay": -5.996886,
"finish_merge__cpu__total": 4.61,
"finish_merge__mem__peak": 559880.0,
"finish_merge__runtime__total": "0:05.07",
"floorplan__cpu__total": 585.48,
"floorplan__design__core__area": 5654.27,
"floorplan__design__die__area": 6307.06,
"floorplan__design__instance__area": 2276.04,
"floorplan__design__instance__area__cover": 0,
"floorplan__design__instance__area__macros": 0,
"floorplan__design__instance__area__padcells": 0,
"floorplan__design__instance__area__stdcell": 2276.04,
"floorplan__design__instance__count": 18331,
"floorplan__design__instance__count__cover": 0,
"floorplan__design__instance__count__hold_buffer": 0,
"floorplan__design__instance__count__macros": 0,
"floorplan__design__instance__count__padcells": 0,
"floorplan__design__instance__count__setup_buffer": 3,
"floorplan__design__instance__count__stdcell": 18331,
"floorplan__design__instance__utilization": 0.402535,
"floorplan__design__instance__utilization__stdcell": 0.402535,
"floorplan__design__io": 264,
"floorplan__design__rows": 278,
"floorplan__design__rows:asap7sc7p5t": 278,
"floorplan__design__sites": 387810,
"floorplan__design__sites:asap7sc7p5t": 387810,
"floorplan__flow__errors__count": 0,
"floorplan__flow__warnings__count": 484,
"floorplan__mem__peak": 3039120.0,
"floorplan__power__internal__total": 0.0178269,
"floorplan__power__leakage__total": 1.65498e-06,
"floorplan__power__switching__total": 0.0151741,
"floorplan__power__total": 0.0330026,
"floorplan__runtime__total": "9:47.66",
"floorplan__timing__setup__tns": 0,
"floorplan__timing__setup__ws": 0.170641,
"floorplan_io__cpu__total": 2.17,
"floorplan_io__mem__peak": 237568.0,
"floorplan_io__runtime__total": "0:02.36",
"floorplan_macro__cpu__total": 2.18,
"floorplan_macro__mem__peak": 237312.0,
"floorplan_macro__runtime__total": "0:02.39",
"floorplan_pdn__cpu__total": 2.51,
"floorplan_pdn__mem__peak": 241356.0,
"floorplan_pdn__runtime__total": "0:02.73",
"floorplan_tap__cpu__total": 2.07,
"floorplan_tap__mem__peak": 226816.0,
"floorplan_tap__runtime__total": "0:02.28",
"flow__errors__count": 0,
"flow__warnings__count": 10,
"globalplace__cpu__total": 1673.62,
"globalplace__design__core__area": 5654.27,
"globalplace__design__die__area": 6307.06,
"globalplace__design__instance__area": 2471.43,
"globalplace__design__instance__area__cover": 0,
"globalplace__design__instance__area__macros": 0,
"globalplace__design__instance__area__padcells": 0,
"globalplace__design__instance__area__stdcell": 2471.43,
"globalplace__design__instance__count": 19330,
"globalplace__design__instance__count__cover": 0,
"globalplace__design__instance__count__macros": 0,
"globalplace__design__instance__count__padcells": 0,
"globalplace__design__instance__count__stdcell": 19330,
"globalplace__design__instance__utilization": 0.43709,
"globalplace__design__instance__utilization__stdcell": 0.43709,
"globalplace__design__io": 264,
"globalplace__design__rows": 278,
"globalplace__design__rows:asap7sc7p5t": 278,
"globalplace__design__sites": 387810,
"globalplace__design__sites:asap7sc7p5t": 387810,
"globalplace__flow__errors__count": 0,
"globalplace__flow__warnings__count": 10,
"globalplace__mem__peak": 3478984.0,
"globalplace__power__internal__total": 0.018272,
"globalplace__power__leakage__total": 1.94505e-06,
"globalplace__power__switching__total": 0.0201947,
"globalplace__power__total": 0.0384687,
"globalplace__runtime__total": "6:32.04",
"globalplace__timing__setup__tns": -25495.9,
"globalplace__timing__setup__ws": -166.769,
"globalplace_io__cpu__total": 2.18,
"globalplace_io__mem__peak": 240640.0,
"globalplace_io__runtime__total": "0:02.39",
"globalplace_skip_io__cpu__total": 981.75,
"globalplace_skip_io__mem__peak": 273736.0,
"globalplace_skip_io__runtime__total": "1:25.45",
"globalroute__antenna__violating__nets": 0,
"globalroute__antenna__violating__pins": 0,
"globalroute__antenna_diodes_count": 0,
"globalroute__clock__skew__hold": 133.021,
"globalroute__clock__skew__setup": 159.792,
"globalroute__cpu__total": 129.62,
"globalroute__design__core__area": 5654.27,
"globalroute__design__die__area": 6307.06,
"globalroute__design__instance__area": 2639.14,
"globalroute__design__instance__area__cover": 0,
"globalroute__design__instance__area__macros": 0,
"globalroute__design__instance__area__padcells": 0,
"globalroute__design__instance__area__stdcell": 2639.14,
"globalroute__design__instance__count": 21541,
"globalroute__design__instance__count__cover": 0,
"globalroute__design__instance__count__hold_buffer": 0,
"globalroute__design__instance__count__macros": 0,
"globalroute__design__instance__count__padcells": 0,
"globalroute__design__instance__count__setup_buffer": 15,
"globalroute__design__instance__count__stdcell": 21541,
"globalroute__design__instance__displacement__max": 0.648,
"globalroute__design__instance__displacement__mean": 0.001,
"globalroute__design__instance__displacement__total": 25.38,
"globalroute__design__instance__utilization": 0.466752,
"globalroute__design__instance__utilization__stdcell": 0.466752,
"globalroute__design__io": 264,
"globalroute__design__rows": 278,
"globalroute__design__rows:asap7sc7p5t": 278,
"globalroute__design__sites": 387810,
"globalroute__design__sites:asap7sc7p5t": 387810,
"globalroute__design__violations": 0,
"globalroute__flow__errors__count": 0,
"globalroute__flow__warnings__count": 12,
"globalroute__mem__peak": 897216.0,
"globalroute__power__internal__total": 0.0204573,
"globalroute__power__leakage__total": 2.03126e-06,
"globalroute__power__switching__total": 0.0224408,
"globalroute__power__total": 0.0429002,
"globalroute__route__wirelength__estimated": 94576,
"globalroute__runtime__total": "1:44.99",
"globalroute__timing__clock__slack": -43.838,
"globalroute__timing__drv__hold_violation_count": 0,
"globalroute__timing__drv__max_cap": 0,
"globalroute__timing__drv__max_cap_limit": 0.419739,
"globalroute__timing__drv__max_fanout": 0,
"globalroute__timing__drv__max_fanout_limit": 0,
"globalroute__timing__drv__max_slew": 0,
"globalroute__timing__drv__max_slew_limit": 0.196596,
"globalroute__timing__drv__setup_violation_count": 36,
"globalroute__timing__setup__tns": -764.286,
"globalroute__timing__setup__ws": -43.8383,
"placeopt__cpu__total": 140.63,
"placeopt__design__core__area": 5654.27,
"placeopt__design__die__area": 6307.06,
"placeopt__design__instance__area": 2564.9,
"placeopt__design__instance__area__cover": 0,
"placeopt__design__instance__area__macros": 0,
"placeopt__design__instance__area__padcells": 0,
"placeopt__design__instance__area__stdcell": 2564.9,
"placeopt__design__instance__count": 21241,
"placeopt__design__instance__count__cover": 0,
"placeopt__design__instance__count__macros": 0,
"placeopt__design__instance__count__padcells": 0,
"placeopt__design__instance__count__stdcell": 21241,
"placeopt__design__instance__utilization": 0.453622,
"placeopt__design__instance__utilization__stdcell": 0.453622,
"placeopt__design__io": 264,
"placeopt__design__rows": 278,
"placeopt__design__rows:asap7sc7p5t": 278,
"placeopt__design__sites": 387810,
"placeopt__design__sites:asap7sc7p5t": 387810,
"placeopt__flow__errors__count": 0,
"placeopt__flow__warnings__count": 10,
"placeopt__mem__peak": 1233200.0,
"placeopt__power__internal__total": 0.0186429,
"placeopt__power__leakage__total": 1.96045e-06,
"placeopt__power__switching__total": 0.0203373,
"placeopt__power__total": 0.0389822,
"placeopt__runtime__total": "2:21.47",
"placeopt__timing__drv__floating__nets": 0,
"placeopt__timing__drv__floating__pins": 0,
"placeopt__timing__drv__hold_violation_count": 0,
"placeopt__timing__drv__max_cap": 0,
"placeopt__timing__drv__max_cap_limit": 0.427192,
"placeopt__timing__drv__max_fanout": 0,
"placeopt__timing__drv__max_fanout_limit": 0,
"placeopt__timing__drv__max_slew": 0,
"placeopt__timing__drv__max_slew_limit": 0.0543873,
"placeopt__timing__drv__setup_violation_count": 255,
"placeopt__timing__setup__tns": -25503.4,
"placeopt__timing__setup__ws": -166.534,
"run__flow__design": "ibex",
"run__flow__generate_date": "2025-01-28 11:14",
"run__flow__metrics_version": "Metrics_2.1.2",
"run__flow__openroad_commit": "N/A",
"run__flow__openroad_version": "6d69029d9813cb8f1c0e3c1dce919cead101a2c5",
"run__flow__platform": "asap7",
"run__flow__platform__capacitance_units": "1fF",
"run__flow__platform__current_units": "1mA",
"run__flow__platform__distance_units": "1um",
"run__flow__platform__power_units": "1pW",
"run__flow__platform__resistance_units": "1kohm",
"run__flow__platform__time_units": "1ps",
"run__flow__platform__voltage_units": "1v",
"run__flow__platform_commit": "6217504d39d7f0785e87380673de9e8264e1f955",
"run__flow__scripts_commit": "6217504d39d7f0785e87380673de9e8264e1f955",
"run__flow__uuid": "17dde336-608c-44d7-983e-7d37057dcfc3",
"run__flow__variant": "base",
"synth__cpu__total": 58.31,
"synth__design__instance__area__stdcell": 2275.12152,
"synth__design__instance__count__stdcell": 18332.0,
"synth__mem__peak": 194816.0,
"synth__runtime__total": "0:58.69",
"total_time": "0:29:21.790000"
}

70
examples/saif_example/saif_trace_example/rules-base.json Normal file
View File

@ -0,0 +1,70 @@
{
"synth__design__instance__area__stdcell": {
"value": 2616.39,
"compare": "<="
},
"constraints__clocks__count": {
"value": 1,
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 2950,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 24427,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 2124,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 2124,
"compare": "<="
},
"globalroute__antenna_diodes_count": {
"value": 0,
"compare": "<="
},
"detailedroute__route__wirelength": {
"value": 132532,
"compare": "<="
},
"detailedroute__route__drc_errors": {
"value": 0,
"compare": "<="
},
"detailedroute__antenna__violating__nets": {
"value": 0,
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
"value": 0,
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -127.02,
"compare": ">="
},
"finish__design__instance__area": {
"value": 3035,
"compare": "<="
},
"finish__timing__drv__setup_violation_count": {
"value": 1062,
"compare": "<="
},
"finish__timing__drv__hold_violation_count": {
"value": 100,
"compare": "<="
},
"finish__timing__wns_percent_delay": {
"value": -17.16,
"compare": ">="
}
}

5
examples/saif_example/src/saif_trace_example/BUILD.bazel Normal file
View File

@ -0,0 +1,5 @@
filegroup(
name = "verilog",
srcs = glob(include = ["*.v"]),
visibility = ["//visibility:public"],
)

51
examples/saif_example/src/saif_trace_example/counter.v Normal file
View File

@ -0,0 +1,51 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2025 by Antmicro. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module t (
// Outputs
state,
// Inputs
clk);
input clk;
reg rst;
output [7:0] state;
counter c0 (
.clk (clk),
.rst (rst),
.out (state));
int cyc;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 0) begin
rst <= 1;
end
else if (cyc == 10) begin
rst <= 0;
end
else if (cyc == 11) begin
rst <= 1;
end
end
endmodule
module counter (
input clk,
input rst,
output reg[7:0] out);
always @ (posedge clk) begin
if (!rst)
out <= 0;
else
out <= out + 1;
end
endmodule