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Commentary: Changes update

This commit is contained in:
Wilson Snyder 2025-09-26 20:49:27 -04:00
parent 500312c050
commit ebee20c47d
4 changed files with 8 additions and 2 deletions
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@ -13,7 +13,7 @@ Verilator 5.041 devel
**Other:** **Other:**
* Add error on parameter values from hierarchical paths (#1626) (#6456). [Luca Rufer] * Add HIERPARAM error on parameter values from hierarchical paths (#1626) (#6456) (#6484). [Todd Strader] [Luca Rufer]
* Add error on zero/negative unpacked dimensions (#1642). [Stefan Wallentowitz] * Add error on zero/negative unpacked dimensions (#1642). [Stefan Wallentowitz]
* Add verilator_gantt profiling of DPI imports (#3084). [Geza Lore] * Add verilator_gantt profiling of DPI imports (#3084). [Geza Lore]
* Add ASSIGNEQEXPR when use `=` inside expressions (#5567). [Ethan Sifferman] * Add ASSIGNEQEXPR when use `=` inside expressions (#5567). [Ethan Sifferman]
@ -28,6 +28,7 @@ Verilator 5.041 devel
* Support class package reference on pattern keys (#5653). [Todd Strader] * Support class package reference on pattern keys (#5653). [Todd Strader]
* Support digits in `$sscanf` field width formats (#6083). [Iztok Jeras] * Support digits in `$sscanf` field width formats (#6083). [Iztok Jeras]
* Support pure functions in sensitivity lists (#6393). [Krzysztof Bieganski, Antmicro Ltd.] * Support pure functions in sensitivity lists (#6393). [Krzysztof Bieganski, Antmicro Ltd.]
* Support simple alias statements (#6339). [Ryszard Rozak, Antmicro Ltd.]
* Improve automatic selection of logic for DFG synthesis (#6370). [Geza Lore] * Improve automatic selection of logic for DFG synthesis (#6370). [Geza Lore]
* Improve `covergroup with function sample` handling (#6387). [Jakub Wasilewski] * Improve `covergroup with function sample` handling (#6387). [Jakub Wasilewski]
* Improve DFG type system (#6390). [Geza Lore] * Improve DFG type system (#6390). [Geza Lore]

4
README.rst
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@ -37,6 +37,7 @@ Welcome to Verilator
* - **Widely Used** * - **Widely Used**
* Wide industry and academic deployment * Wide industry and academic deployment
* Out-of-the-box support from Arm and RISC-V vendor IP * Out-of-the-box support from Arm and RISC-V vendor IP
* Over 700 contributors
- |verilator usage| - |verilator usage|
* - |verilator community| * - |verilator community|
- **Community Driven & Openly Licensed** - **Community Driven & Openly Licensed**
@ -137,6 +138,9 @@ Related Projects
- `Icarus Verilog`_ - Icarus is a highly-featured interpreted Verilog - `Icarus Verilog`_ - Icarus is a highly-featured interpreted Verilog
simulator. If Verilator does not support your needs, perhaps Icarus may. simulator. If Verilator does not support your needs, perhaps Icarus may.
_ `Surfer <https://surfer-project.org/>`_, Web or offline waveform viewer
for Verilator traces.
Open License Open License
============ ============

2
docs/guide/install.rst
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@ -157,7 +157,7 @@ Those developing Verilator itself also need these (see internals.rst):
.. code-block:: bash .. code-block:: bash
sudo apt-get install clang clang-format-18 cmake gdb gprof graphviz lcov sudo apt-get install clang clang-format-18 cmake gdb gprof graphviz lcov
sudo apt-get install python3-clang python3-distro yapf3 bear jq sudo apt-get install python3-clang python3-distro pipx yapf3 bear jq
python3 -m venv --system-site-packages ~/.verilator_pyenv python3 -m venv --system-site-packages ~/.verilator_pyenv
source ~/.verilator_pyenv/bin/activate source ~/.verilator_pyenv/bin/activate
pip3 install sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe gersemi mbake ruff pip3 install sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe gersemi mbake ruff

1
docs/spelling.txt
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@ -849,6 +849,7 @@ miree
mis mis
misconnected misconnected
misconversion misconversion
misdetecting
misoptimized misoptimized
missized missized
mk mk