Support for simple alias statements (#6339)
This commit is contained in:
Ryszard Rozak
GitHub
parent
4ad1dde723
commit
500312c050
|
|
@ -473,14 +473,14 @@ public:
|
|||
inline bool hasCombo() const;
|
||||
};
|
||||
class AstAlias final : public AstNode {
|
||||
// Alias (currently only used internally, not as the SV 'alias' construct).
|
||||
// Alias statement
|
||||
// All references to the LHS are treated as references to the RHS
|
||||
// If both sides are wires, there's no LHS vs RHS,
|
||||
// @astgen op1 := rhsp : AstVarRef
|
||||
// @astgen op2 := lhsp : AstVarRef
|
||||
// @astgen op1 := rhsp : AstNodeExpr
|
||||
// @astgen op2 := lhsp : AstNodeExpr
|
||||
|
||||
public:
|
||||
AstAlias(FileLine* fl, AstVarRef* lhsp, AstVarRef* rhsp)
|
||||
AstAlias(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
|
||||
: ASTGEN_SUPER_Alias(fl) {
|
||||
this->lhsp(lhsp);
|
||||
this->rhsp(rhsp);
|
||||
|
|
|
|||
|
|
@ -131,6 +131,8 @@ class LinkDotState final {
|
|||
// AstNodeModule::user2() // bool. Currently processing for recursion check
|
||||
// ... Note maybe more than one, as can be multiple hierarchy places
|
||||
// AstVarScope::user2p() // AstVarScope*. Base alias for AstInline of this signal
|
||||
// AstAssignW::user2() // bool. Created for aliases handling.
|
||||
// ... Don't replace var refs if set
|
||||
// AstVar::user2p() // AstFTask*. If a function variable, the task
|
||||
// that links to the variable
|
||||
// AstVar::user4() // bool. True if port set for this variable
|
||||
|
|
@ -2214,6 +2216,26 @@ class LinkDotScopeVisitor final : public VNVisitor {
|
|||
const AstScope* m_scopep = nullptr; // The current scope
|
||||
VSymEnt* m_modSymp = nullptr; // Symbol entry for current module
|
||||
|
||||
// METHODS
|
||||
public:
|
||||
// getAliasVarScopep and setAliasVarScope implement disjoint-set data structure.
|
||||
// This algorithm is needed for the case when multiple alias statements
|
||||
// reference partially the same variables.
|
||||
static AstVarScope* getAliasVarScopep(AstVarScope* const vscp) {
|
||||
if (vscp->user2p() && vscp != vscp->user2p()) {
|
||||
AstVarScope* const aliasp = getAliasVarScopep(VN_AS(vscp->user2p(), VarScope));
|
||||
vscp->user2p(aliasp);
|
||||
return aliasp;
|
||||
} else {
|
||||
return vscp;
|
||||
}
|
||||
}
|
||||
|
||||
private:
|
||||
void setAliasVarScope(AstVarScope* const vscp, AstVarScope* const aliasp) {
|
||||
getAliasVarScopep(vscp)->user2p(getAliasVarScopep(aliasp));
|
||||
}
|
||||
|
||||
// VISITORS
|
||||
void visit(AstNetlist* nodep) override { // ScopeVisitor::
|
||||
// Recurse..., backward as must do packages before using packages
|
||||
|
|
@ -2289,24 +2311,17 @@ class LinkDotScopeVisitor final : public VNVisitor {
|
|||
// No recursion, we don't want to pick up variables
|
||||
}
|
||||
void visit(AstAlias* nodep) override { // ScopeVisitor::
|
||||
// Track aliases created by V3Inline; if we get a VARXREF(aliased_from)
|
||||
// we'll need to replace it with a VARXREF(aliased_to)
|
||||
// Track aliases; if we get a NODEVARREF(aliased_from)
|
||||
// we'll need to replace it with a NODEVARREF(aliased_to)
|
||||
UINFOTREE(9, nodep, "", "alias");
|
||||
AstVarRef* const lhsp = nodep->lhsp();
|
||||
AstVarRef* const rhsp = nodep->rhsp();
|
||||
AstVarRef* const lhsp = VN_AS(nodep->lhsp(), VarRef);
|
||||
AstVarRef* const rhsp = VN_AS(nodep->rhsp(), VarRef);
|
||||
AstVarScope* const fromVscp = lhsp->varScopep();
|
||||
AstVarScope* const toVscp = rhsp->varScopep();
|
||||
UASSERT_OBJ(fromVscp && toVscp, nodep, "Bad alias scopes");
|
||||
fromVscp->user2p(toVscp);
|
||||
|
||||
// Replace alias with an assignment. The LHS might still be references from otuside,
|
||||
// eg throught the VPI, and is traced, so we need the value to propagate.
|
||||
// TODO: this means external writes to the LHS (e.g.: through the VPI) don't work
|
||||
AstAssignW* const newp
|
||||
= new AstAssignW{nodep->fileline(), lhsp->unlinkFrBack(), rhsp->unlinkFrBack()};
|
||||
nodep->replaceWith(newp);
|
||||
VL_DO_DANGLING(pushDeletep(nodep), nodep);
|
||||
iterateChildren(newp);
|
||||
setAliasVarScope(fromVscp, toVscp);
|
||||
iterateChildren(nodep);
|
||||
pushDeletep(nodep->unlinkFrBack());
|
||||
}
|
||||
void visit(AstAssignVarScope* nodep) override { // ScopeVisitor::
|
||||
UINFO(5, "ASSIGNVARSCOPE " << nodep);
|
||||
|
|
@ -2535,6 +2550,8 @@ class LinkDotResolveVisitor final : public VNVisitor {
|
|||
AstNode* m_lastDeferredp = nullptr; // Last node which requested a revisit of its module
|
||||
AstNodeDType* m_packedArrayDtp = nullptr; // Datatype reference for packed array
|
||||
bool m_inPackedArray = false; // Currently traversing a packed array tree
|
||||
bool m_replaceWithAlias
|
||||
= true; // Replace VarScope with an alias. Used in the handling of AstAlias
|
||||
|
||||
struct DotStates final {
|
||||
DotPosition m_dotPos; // Scope part of dotted resolution
|
||||
|
|
@ -3983,6 +4000,14 @@ class LinkDotResolveVisitor final : public VNVisitor {
|
|||
<< nodep->prettyNameQ());
|
||||
}
|
||||
}
|
||||
AstVarScope* vscp = nodep->varScopep();
|
||||
if (vscp && vscp->user2p() != vscp && m_replaceWithAlias) {
|
||||
vscp = LinkDotScopeVisitor::getAliasVarScopep(vscp);
|
||||
nodep->varp(vscp->varp());
|
||||
nodep->varScopep(vscp);
|
||||
updateVarUse(nodep->varp());
|
||||
UINFO(7, indent() << "Resolved " << nodep); // Also prints taskp
|
||||
}
|
||||
}
|
||||
void visit(AstVarXRef* nodep) override {
|
||||
// VarRef: Resolve its reference
|
||||
|
|
@ -4099,9 +4124,8 @@ class LinkDotResolveVisitor final : public VNVisitor {
|
|||
<< nodep->warnContextPrimary()
|
||||
<< okSymp->cellErrorScopes(nodep));
|
||||
} else {
|
||||
while (vscp->user2p()) { // If V3Inline aliased it, pick up the new signal
|
||||
UINFO(7, indent() << "Resolved pre-alias " << vscp); // Also prints taskp
|
||||
vscp = VN_AS(vscp->user2p(), VarScope);
|
||||
if (vscp->user2p() && m_replaceWithAlias) {
|
||||
vscp = LinkDotScopeVisitor::getAliasVarScopep(vscp);
|
||||
}
|
||||
// Convert the VarXRef to a VarRef, so we don't need
|
||||
// later optimizations to deal with VarXRef.
|
||||
|
|
@ -4185,6 +4209,25 @@ class LinkDotResolveVisitor final : public VNVisitor {
|
|||
"Input/output/inout does not appear in port list: " << nodep->prettyNameQ());
|
||||
}
|
||||
}
|
||||
void visit(AstVarScope* nodep) override {
|
||||
LINKDOT_VISIT_START();
|
||||
checkNoDot(nodep);
|
||||
iterateChildren(nodep);
|
||||
AstVarScope* aliasp = LinkDotScopeVisitor::getAliasVarScopep(nodep);
|
||||
if (aliasp && aliasp != nodep) {
|
||||
// Aliased variable might still be references from outside,
|
||||
// eg through the VPI, and is traced, so we need the value to propagate.
|
||||
// TODO: this means external writes to the LHS (e.g.: through the VPI) don't work
|
||||
AstAssignW* const assignp = new AstAssignW{
|
||||
nodep->fileline(), new AstVarRef{nodep->fileline(), nodep, VAccess::WRITE},
|
||||
new AstVarRef{nodep->fileline(), aliasp, VAccess::READ}};
|
||||
assignp->user2(true);
|
||||
nodep->addNextHere(assignp);
|
||||
// Propagate attributes of the replaced variable,
|
||||
// because all references to it are replaced with references to the alias variable
|
||||
aliasp->varp()->propagateAttrFrom(nodep->varp());
|
||||
}
|
||||
}
|
||||
void visit(AstNodeFTaskRef* nodep) override {
|
||||
if (nodep->user3SetOnce()) return;
|
||||
LINKDOT_VISIT_START();
|
||||
|
|
@ -5049,6 +5092,14 @@ class LinkDotResolveVisitor final : public VNVisitor {
|
|||
|
||||
void visit(AstAttrOf* nodep) override { iterateChildren(nodep); }
|
||||
|
||||
void visit(AstAssignW* nodep) override {
|
||||
LINKDOT_VISIT_START();
|
||||
checkNoDot(nodep);
|
||||
VL_RESTORER(m_replaceWithAlias);
|
||||
if (nodep->user2()) m_replaceWithAlias = false;
|
||||
iterateChildren(nodep);
|
||||
}
|
||||
|
||||
void visit(AstNode* nodep) override {
|
||||
VL_RESTORER(m_inPackedArray);
|
||||
if (VN_IS(nodep, PackArrayDType)) {
|
||||
|
|
|
|||
|
|
@ -137,6 +137,11 @@ class LinkLValueVisitor final : public VNVisitor {
|
|||
}
|
||||
}
|
||||
}
|
||||
void visit(AstAlias* nodep) override {
|
||||
VL_RESTORER(m_setRefLvalue);
|
||||
m_setRefLvalue = VAccess::READWRITE;
|
||||
iterateChildren(nodep);
|
||||
}
|
||||
void visit(AstInitialStatic* nodep) override {
|
||||
VL_RESTORER(m_inInitialStatic);
|
||||
m_inInitialStatic = true;
|
||||
|
|
|
|||
|
|
@ -435,6 +435,7 @@ class TristateVisitor final : public TristateBaseVisitor {
|
|||
VarToAssignsMap m_assigns; // Assigns in current module
|
||||
int m_unique = 0;
|
||||
bool m_alhs = false; // On LHS of assignment
|
||||
bool m_inAlias = false; // Inside alias statement
|
||||
VStrength m_currentStrength = VStrength::STRONG; // Current strength of assignment,
|
||||
// Used only on LHS of assignment
|
||||
const AstNode* m_logicp = nullptr; // Current logic being built
|
||||
|
|
@ -1360,6 +1361,22 @@ class TristateVisitor final : public TristateBaseVisitor {
|
|||
}
|
||||
void visit(AstAssignW* nodep) override { visitAssign(nodep); }
|
||||
void visit(AstAssign* nodep) override { visitAssign(nodep); }
|
||||
void visit(AstAlias* nodep) override {
|
||||
VL_RESTORER(m_alhs);
|
||||
VL_RESTORER(m_inAlias);
|
||||
m_inAlias = true;
|
||||
if (m_graphing) {
|
||||
if (nodep->user2() & U2_GRAPHING) return;
|
||||
m_alhs = true; // In AstAlias both sides should be considered as lhs
|
||||
iterateChildren(nodep);
|
||||
associateLogic(nodep->rhsp(), nodep);
|
||||
associateLogic(nodep, nodep->rhsp());
|
||||
associateLogic(nodep, nodep->lhsp());
|
||||
associateLogic(nodep->lhsp(), nodep);
|
||||
} else {
|
||||
iterateChildren(nodep);
|
||||
}
|
||||
}
|
||||
|
||||
void visitCaseEq(AstNodeBiop* nodep, bool neq) {
|
||||
if (m_graphing) {
|
||||
|
|
@ -1753,6 +1770,17 @@ class TristateVisitor final : public TristateBaseVisitor {
|
|||
// any tristate logic on the driver.
|
||||
if (nodep->access().isWriteOrRW() && m_tgraph.isTristate(nodep->varp())) {
|
||||
UINFO(9, " Ref-to-lvalue " << nodep);
|
||||
if (m_inAlias) {
|
||||
if (nodep->varp()->direction().isAny()) {
|
||||
nodep->v3warn(E_UNSUPPORTED, "Unsupported: Port as alias argument: "
|
||||
<< nodep->prettyNameQ());
|
||||
} else {
|
||||
nodep->v3warn(E_UNSUPPORTED,
|
||||
"Unsupported: Tristate variable referenced in alias: "
|
||||
<< nodep->prettyNameQ());
|
||||
}
|
||||
return;
|
||||
}
|
||||
UASSERT_OBJ(!nodep->access().isRW(), nodep, "Tristate unexpected on R/W access");
|
||||
m_tgraph.didProcess(nodep);
|
||||
mapInsertLhsVarRef(nodep);
|
||||
|
|
|
|||
|
|
@ -228,6 +228,7 @@ class WidthVisitor final : public VNVisitor {
|
|||
TableMap m_tableMap; // Created tables so can remove duplicates
|
||||
std::map<const AstNodeDType*, AstQueueDType*>
|
||||
m_queueDTypeIndexed; // Queues with given index type
|
||||
std::unordered_set<AstVar*> m_aliasedVars; // Variables referenced in alias
|
||||
|
||||
static constexpr int ENUM_LOOKUP_BITS = 16; // Maximum # bits to make enum lookup table
|
||||
|
||||
|
|
@ -1188,6 +1189,54 @@ class WidthVisitor final : public VNVisitor {
|
|||
}
|
||||
}
|
||||
|
||||
void visit(AstAlias* nodep) override {
|
||||
if (!nodep->didWidthAndSet()) {
|
||||
userIterate(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
|
||||
userIterate(nodep->rhsp(), WidthVP{SELF, BOTH}.p());
|
||||
}
|
||||
|
||||
const auto checkIfExprOk = [this](const AstNodeExpr* const exprp) {
|
||||
if (VN_IS(exprp, VarXRef)) {
|
||||
exprp->v3error("Hierarchical reference used for net alias (IEEE 1800-2023 10.11)");
|
||||
return false;
|
||||
}
|
||||
|
||||
const AstVarRef* const varRefp = VN_CAST(exprp, VarRef);
|
||||
if (!varRefp) {
|
||||
exprp->v3warn(
|
||||
E_UNSUPPORTED,
|
||||
"Unsupported: Operand of alias statement is not a variable reference");
|
||||
return false;
|
||||
}
|
||||
AstVar* const varp = varRefp->varp();
|
||||
if (!varp->isNet()) {
|
||||
exprp->v3error("Only nets are allowed in alias (IEEE 1800-2023 10.11): "
|
||||
<< varp->prettyNameQ());
|
||||
return false;
|
||||
}
|
||||
if (m_aliasedVars.find(varp) != m_aliasedVars.end()) {
|
||||
varRefp->v3error("Alias is specified more than once (IEEE 1800-2023 10.11): "
|
||||
<< varp->prettyNameQ());
|
||||
return false;
|
||||
} else {
|
||||
m_aliasedVars.insert(varp);
|
||||
}
|
||||
return true;
|
||||
};
|
||||
|
||||
const bool lhsOk = checkIfExprOk(nodep->lhsp());
|
||||
const bool rhsOk = checkIfExprOk(nodep->rhsp());
|
||||
if (!lhsOk || !rhsOk) return;
|
||||
|
||||
const AstNodeDType* const lhsDtypep = nodep->lhsp()->dtypep();
|
||||
const AstNodeDType* const rhsDtypep = nodep->rhsp()->dtypep();
|
||||
if (!lhsDtypep->similarDType(rhsDtypep)) {
|
||||
nodep->v3error("Incompatible data types of nets used for net alias, got "
|
||||
<< lhsDtypep->prettyDTypeNameQ() << " and "
|
||||
<< rhsDtypep->prettyDTypeNameQ());
|
||||
}
|
||||
}
|
||||
|
||||
void visit(AstWildcardSel* nodep) override {
|
||||
// Signed/Real: Output type based on array-declared type; binary operator
|
||||
if (m_vup->prelim()) {
|
||||
|
|
|
|||
|
|
@ -2606,9 +2606,7 @@ module_common_item<nodep>: // ==IEEE: module_common_item
|
|||
| assertion_item { $$ = $1; }
|
||||
| bind_directive { $$ = $1; }
|
||||
| continuous_assign { $$ = $1; }
|
||||
// // IEEE: net_alias
|
||||
| yALIAS variable_lvalue aliasEqList ';'
|
||||
{ $$ = nullptr; BBUNSUP($1, "Unsupported: alias statements"); DEL($2); }
|
||||
| net_alias { $$ = $1; }
|
||||
| initial_construct { $$ = $1; }
|
||||
| final_construct { $$ = $1; }
|
||||
| always_construct { $$ = $1; }
|
||||
|
|
@ -2638,6 +2636,21 @@ initial_construct<nodep>: // IEEE: initial_construct
|
|||
yINITIAL stmtBlock { $$ = new AstInitial{$1, $2}; }
|
||||
;
|
||||
|
||||
|
||||
net_alias<nodep>: // IEEE: net_alias
|
||||
yALIAS variable_lvalue aliasEqList ';'
|
||||
{ if ($3->nextp()) {
|
||||
BBUNSUP($1, "Unsupported: alias statements with more than 2 operands");
|
||||
$3->nextp()->unlinkFrBackWithNext()->deleteTree();
|
||||
}
|
||||
$$ = new AstAlias{$1, $2, $3}; }
|
||||
;
|
||||
|
||||
aliasEqList<nodeExprp>: // IEEE: part of net_alias
|
||||
'=' variable_lvalue { $$ = $2; }
|
||||
| aliasEqList '=' variable_lvalue { $$ = $1->addNext($3); }
|
||||
;
|
||||
|
||||
final_construct<nodep>: // IEEE: final_construct
|
||||
yFINAL stmtBlock { $$ = new AstFinal{$1, $2}; }
|
||||
;
|
||||
|
|
@ -2660,11 +2673,6 @@ defaultDisable<nodep>: // IEEE: part of module_/checker_or_generate_item_declar
|
|||
{ $$ = new AstDefaultDisable{$1, $4}; }
|
||||
;
|
||||
|
||||
aliasEqList: // IEEE: part of net_alias
|
||||
'=' variable_lvalue { }
|
||||
| aliasEqList '=' variable_lvalue { }
|
||||
;
|
||||
|
||||
bind_directive<nodep>: // ==IEEE: bind_directive + bind_target_scope
|
||||
// // ';' - Note IEEE grammar is wrong, includes extra ';'
|
||||
// // - it's already in module_instantiation
|
||||
|
|
|
|||
|
|
@ -1,5 +0,0 @@
|
|||
%Error-UNSUPPORTED: t/t_alias2_unsup.v:39:4: Unsupported: alias statements
|
||||
39 | alias b = {a[3:0],a[7:4]};
|
||||
| ^~~~~
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Error: Exiting due to
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
|
||||
//
|
||||
// Simple bi-directional alias test.
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2013 by Jeremy Bennett.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
// Values to swap and locations for the swapped values.
|
||||
reg [31:0] x = 32'ha5a5a5a5;
|
||||
wire [31:0] y;
|
||||
|
||||
testit testi_i (.a (x[7:0]),
|
||||
.b (y[31:24]));
|
||||
|
||||
always @ (posedge clk) begin
|
||||
x <= {x[30:0],1'b0};
|
||||
$write("x = %x, y = %x\n", x, y);
|
||||
|
||||
if (x[3:0] != 4'h0) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
// Swap the byte order of two args.
|
||||
module testit (input wire [7:0] a,
|
||||
output wire [7:0] b
|
||||
);
|
||||
|
||||
alias b = {a[3:0],a[7:4]};
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
%Error: t/t_alias_cyclic_bad.v:18:13: Alias is specified more than once (IEEE 1800-2023 10.11): 'a'
|
||||
: ... note: In instance 't'
|
||||
18 | alias a = a;
|
||||
| ^
|
||||
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
|
||||
%Error: t/t_alias_cyclic_bad.v:19:9: Alias is specified more than once (IEEE 1800-2023 10.11): 'a'
|
||||
: ... note: In instance 't'
|
||||
19 | alias a = b;
|
||||
| ^
|
||||
%Error: t/t_alias_cyclic_bad.v:20:9: Alias is specified more than once (IEEE 1800-2023 10.11): 'b'
|
||||
: ... note: In instance 't'
|
||||
20 | alias b = a;
|
||||
| ^
|
||||
%Error: t/t_alias_cyclic_bad.v:20:13: Alias is specified more than once (IEEE 1800-2023 10.11): 'a'
|
||||
: ... note: In instance 't'
|
||||
20 | alias b = a;
|
||||
| ^
|
||||
%Error: Exiting due to
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('vlt')
|
||||
|
||||
test.lint(fails=True, expect_filename=test.golden_filename)
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
|
||||
//
|
||||
// Simple bi-directional transitive alias test.
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2025 by Antmicro.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ( /*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire [31:0] a = 32'hdeadbeef;
|
||||
wire [31:0] b;
|
||||
|
||||
alias a = a;
|
||||
alias a = b;
|
||||
alias b = a;
|
||||
|
||||
always @(posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("a = %x, b = %x\n", a, b);
|
||||
`endif
|
||||
if (b != 32'hdeadbeef) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2024 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile()
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2025 by Antmicro.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ( /*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire [15:0] a, b;
|
||||
|
||||
integer cyc = 0;
|
||||
|
||||
alias a = b;
|
||||
|
||||
always @(posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc == 1) begin
|
||||
force a = 16'h1234;
|
||||
if (a != 16'h1234 || a != b) $stop;
|
||||
release a;
|
||||
end else if (cyc == 2) begin
|
||||
force b = 16'h5678;
|
||||
if (a != 16'h5678 || a != b) $stop;
|
||||
release b;
|
||||
end else if (cyc == 3) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
%Error: t/t_alias_hier_ref_bad.v:18:19: Hierarchical reference used for net alias (IEEE 1800-2023 10.11)
|
||||
: ... note: In instance 't'
|
||||
18 | alias a = sub_i.btw;
|
||||
| ^~~
|
||||
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
|
||||
%Error: Exiting due to
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('vlt')
|
||||
|
||||
test.lint(fails=True, expect_filename=test.golden_filename)
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
|
||||
//
|
||||
// Alias type check error test.
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2025 by Antmicro.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ( /*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
reg [15:0] out;
|
||||
wire [15:0] a;
|
||||
|
||||
alias a = sub_i.btw;
|
||||
|
||||
sub sub_i (
|
||||
.clk(clk),
|
||||
.out(out)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
module sub (
|
||||
input clk,
|
||||
output wire [15:0] out
|
||||
);
|
||||
|
||||
reg [31:0] counter = 32'h0;
|
||||
wire [15:0] btw;
|
||||
|
||||
assign btw = {counter[15:0]};
|
||||
assign out = btw;
|
||||
|
||||
always @(posedge clk) begin
|
||||
counter += 1;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
%Error-UNSUPPORTED: t/t_alias_ports_unsup.v:38:13: Unsupported: Port as alias argument: 'b'
|
||||
: ... note: In instance 't.s'
|
||||
38 | alias a = b;
|
||||
| ^
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Error-UNSUPPORTED: t/t_alias_ports_unsup.v:38:9: Unsupported: Port as alias argument: 'a'
|
||||
: ... note: In instance 't.s'
|
||||
38 | alias a = b;
|
||||
| ^
|
||||
%Error: Exiting due to
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2025 by Antmicro.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ( /*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire [31:0] a, b;
|
||||
|
||||
integer cyc = 0;
|
||||
assign a = cyc;
|
||||
|
||||
sub s (
|
||||
.a(a),
|
||||
.b(b)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (a != cyc) $stop;
|
||||
if (b != cyc) $stop;
|
||||
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sub (
|
||||
inout wire [31:0] a,
|
||||
inout wire [31:0] b
|
||||
);
|
||||
alias a = b;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2024 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile()
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2025 by Antmicro.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ( /*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire [31:0] a, b;
|
||||
wire [31:0] x, y;
|
||||
|
||||
integer cyc = 0;
|
||||
|
||||
alias a = b;
|
||||
assign a = cyc;
|
||||
|
||||
alias x = y;
|
||||
assign x[15:0] = cyc[15:0];
|
||||
assign y[31:16] = cyc[31:16];
|
||||
|
||||
sub s (cyc);
|
||||
|
||||
always @(posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (a != cyc) $stop;
|
||||
if (b != cyc) $stop;
|
||||
|
||||
if (x != cyc) $stop;
|
||||
if (y != cyc) $stop;
|
||||
|
||||
if (s.a != cyc) $stop;
|
||||
if (s.b != cyc) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sub (
|
||||
input integer cyc
|
||||
);
|
||||
wire [31:0] a, b;
|
||||
assign a = cyc;
|
||||
alias a = b;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2024 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile()
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2025 by Geza Lore.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ( /*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
sub s ();
|
||||
assign s.a[0] = 0;
|
||||
assign s.b[1] = 1;
|
||||
|
||||
initial begin
|
||||
if (s.a != 2) $stop;
|
||||
if (s.b != 2) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
|
||||
end
|
||||
endmodule
|
||||
|
||||
module sub;
|
||||
wire [1:0] a, b;
|
||||
alias a = b;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
%Error-UNSUPPORTED: t/t_alias_transitive_unsup.v:19:3: Unsupported: alias statements with more than 2 operands
|
||||
19 | alias a = b = c;
|
||||
| ^~~~~
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Error: Exiting due to
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('vlt')
|
||||
|
||||
test.lint(fails=True, expect_filename=test.golden_filename)
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
|
||||
//
|
||||
// Simple bi-directional transitive alias test.
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2025 by Antmicro.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ( /*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire [31:0] a = 32'hdeadbeef;
|
||||
wire [31:0] b;
|
||||
wire [31:0] c;
|
||||
|
||||
alias a = b = c;
|
||||
|
||||
always @(posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("a = %x, b = %x, c = %x\n", a, b, c);
|
||||
`endif
|
||||
if (c != 32'hdeadbeef) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
%Error-UNSUPPORTED: t/t_alias_tristate_unsup.v:17:9: Unsupported: Tristate variable referenced in alias: 'a'
|
||||
: ... note: In instance 't'
|
||||
17 | alias a = b;
|
||||
| ^
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Error: Exiting due to
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2024 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('linter')
|
||||
|
||||
test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2025 by Antmicro.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ( /*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire [31:0] a, b;
|
||||
|
||||
integer cyc = 0;
|
||||
assign a = 'z;
|
||||
alias a = b;
|
||||
|
||||
always @(posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (a !== 'z) $stop;
|
||||
if (b !== 'z) $stop;
|
||||
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
%Error-UNSUPPORTED: t/t_alias_unsup.v:46:4: Unsupported: alias statements
|
||||
46 | alias {a[7:0],a[15:8],a[23:16],a[31:24]} = b;
|
||||
| ^~~~~
|
||||
%Error-UNSUPPORTED: t/t_alias_unsup.v:50:35: Unsupported: Operand of alias statement is not a variable reference
|
||||
: ... note: In instance 't.swap_bwd_i'
|
||||
50 | alias {a[7:0], a[15:8], a[23:16], a[31:24]} = b;
|
||||
| ^
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Error: Exiting due to
|
||||
|
|
|
|||
|
|
@ -6,53 +6,56 @@
|
|||
// any use, without warranty, 2013 by Jeremy Bennett.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
module t ( /*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
// Values to swap and locations for the swapped values.
|
||||
wire [31:0] x_fwd = 32'hdeadbeef;
|
||||
wire [31:0] y_fwd;
|
||||
wire [31:0] x_bwd;
|
||||
wire [31:0] y_bwd = 32'hfeedface;
|
||||
// Values to swap and locations for the swapped values.
|
||||
wire [31:0] x_fwd = 32'hdeadbeef;
|
||||
wire [31:0] y_fwd;
|
||||
wire [31:0] x_bwd;
|
||||
wire [31:0] y_bwd = 32'hfeedface;
|
||||
|
||||
swap swap_fwd_i (.a (x_fwd),
|
||||
.b (y_fwd));
|
||||
swap swap_bwd_i (.a (x_bwd),
|
||||
.b (y_bwd));
|
||||
swap swap_fwd_i (
|
||||
.a(x_fwd),
|
||||
.b(y_fwd)
|
||||
);
|
||||
swap swap_bwd_i (
|
||||
.a(x_bwd),
|
||||
.b(y_bwd)
|
||||
);
|
||||
|
||||
always @ (posedge clk) begin
|
||||
always @(posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write ("x_fwd = %x, y_fwd = %x\n", x_fwd, y_fwd);
|
||||
$write ("x_bwd = %x, y_bwd = %x\n", x_bwd, y_bwd);
|
||||
$write("x_fwd = %x, y_fwd = %x\n", x_fwd, y_fwd);
|
||||
$write("x_bwd = %x, y_bwd = %x\n", x_bwd, y_bwd);
|
||||
`endif
|
||||
if (y_fwd != 32'hefbeadde) $stop;
|
||||
if (x_bwd == 32'hcefaedfe) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
if (y_fwd != 32'hefbeadde) $stop;
|
||||
if (x_bwd != 32'hcefaedfe) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
// Swap the byte order of two args.
|
||||
module swap (
|
||||
inout wire [31:0] a,
|
||||
inout wire [31:0] b
|
||||
);
|
||||
inout wire [31:0] a,
|
||||
inout wire [31:0] b
|
||||
);
|
||||
|
||||
alias {a[7:0],a[15:8],a[23:16],a[31:24]} = b;
|
||||
alias {a[7:0], a[15:8], a[23:16], a[31:24]} = b;
|
||||
|
||||
// Equivalent to
|
||||
// Equivalent to
|
||||
|
||||
// wire [31:0] a_prime;
|
||||
// wire [31:0] b_prime;
|
||||
|
||||
// assign b_prime = {a[7:0],a[15:8],a[23:16],a[31:24]};
|
||||
// assign {a_prime[7:0],a_prime[15:8],a_prime[23:16],a_prime[31:24]} = b;
|
||||
// assign b = b_prime;
|
||||
// assign a = a_prime;
|
||||
// wire [31:0] a_prime;
|
||||
// wire [31:0] b_prime;
|
||||
|
||||
// assign b_prime = {a[7:0],a[15:8],a[23:16],a[31:24]};
|
||||
// assign {a_prime[7:0],a_prime[15:8],a_prime[23:16],a_prime[31:24]} = b;
|
||||
// assign b = b_prime;
|
||||
// assign a = a_prime;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -0,0 +1,10 @@
|
|||
%Error: t/t_alias_var_bad.v:18:9: Only nets are allowed in alias (IEEE 1800-2023 10.11): 'a'
|
||||
: ... note: In instance 't'
|
||||
18 | alias a = b;
|
||||
| ^
|
||||
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
|
||||
%Error: t/t_alias_var_bad.v:18:13: Only nets are allowed in alias (IEEE 1800-2023 10.11): 'b'
|
||||
: ... note: In instance 't'
|
||||
18 | alias a = b;
|
||||
| ^
|
||||
%Error: Exiting due to
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('vlt')
|
||||
|
||||
test.lint(fails=True, expect_filename=test.golden_filename)
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
|
||||
//
|
||||
// Alias width check error test.
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2025 by Antmicro.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ( /*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
logic [31:0] a;
|
||||
logic [31:0] b;
|
||||
|
||||
alias a = b;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
%Error: t/t_alias_width_bad.v:18:3: Incompatible data types of nets used for net alias, got 'logic[1:0]' and 'logic[2:0]'
|
||||
: ... note: In instance 't'
|
||||
18 | alias a = b;
|
||||
| ^~~~~
|
||||
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
|
||||
%Error: Exiting due to
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('vlt')
|
||||
|
||||
test.lint(fails=True, expect_filename=test.golden_filename)
|
||||
|
||||
test.passes()
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
|
||||
//
|
||||
// Alias width check error test.
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2025 by Antmicro.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t ( /*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
wire [1:0] a;
|
||||
wire [2:0] b;
|
||||
|
||||
alias a = b;
|
||||
|
||||
endmodule
|
||||
|
|
@ -21,7 +21,7 @@ test.inline_checks()
|
|||
test.file_grep_not(test.obj_dir + "/coverage.dat", "largeish")
|
||||
|
||||
if test.vlt_all:
|
||||
test.file_grep(test.stats, r'Coverage, Toggle points joined\s+(\d+)', 13)
|
||||
test.file_grep(test.stats, r'Coverage, Toggle points joined\s+(\d+)', 14)
|
||||
|
||||
test.run(cmd=[
|
||||
os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage",
|
||||
|
|
|
|||
|
|
@ -18,9 +18,10 @@ module t (/*AUTOARG*/
|
|||
always @(posedge clk) cyc <= cyc + 1;
|
||||
|
||||
wire net_1;
|
||||
wire [7:0] net_8;
|
||||
wire [7:0] net_8, alias_net_8;
|
||||
assign net_1 = ~cyc[0];
|
||||
assign net_8 = ~cyc[1 +: 8];
|
||||
alias net_8 = alias_net_8;
|
||||
|
||||
always @ (posedge clk) begin
|
||||
$display("%d pre : %x %x", cyc, net_8, net_1);
|
||||
|
|
@ -118,6 +119,7 @@ module t (/*AUTOARG*/
|
|||
end
|
||||
default: begin
|
||||
`checkh ({net_8, net_1}, ~cyc[0 +: 9]);
|
||||
`checkh ({alias_net_8, net_1}, ~cyc[0 +: 9]);
|
||||
end
|
||||
endcase
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ $timescale 1ps $end
|
|||
$var wire 32 $ cyc [31:0] $end
|
||||
$var wire 1 % net_1 $end
|
||||
$var wire 8 & net_8 [7:0] $end
|
||||
$var wire 8 & alias_net_8 [7:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
|
|
|
|||
|
|
@ -31,104 +31,104 @@
|
|||
{"type":"VARSCOPE","name":"clk","addr":"(CB)","loc":"d,13:10,13:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(I)"},
|
||||
{"type":"VARSCOPE","name":"d","addr":"(DB)","loc":"d,14:16,14:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(K)"},
|
||||
{"type":"VARSCOPE","name":"t.q","addr":"(EB)","loc":"d,15:22,15:23","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(L)"},
|
||||
{"type":"VARSCOPE","name":"t.clk","addr":"(FB)","loc":"d,13:10,13:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(M)"},
|
||||
{"type":"VARSCOPE","name":"t.d","addr":"(GB)","loc":"d,14:16,14:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(N)"},
|
||||
{"type":"VARSCOPE","name":"t.between","addr":"(HB)","loc":"d,17:22,17:29","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(O)"},
|
||||
{"type":"VARSCOPE","name":"t.cell1.WIDTH","addr":"(IB)","loc":"d,32:15,32:20","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(P)"},
|
||||
{"type":"VARSCOPE","name":"t.cell1.clk","addr":"(JB)","loc":"d,34:24,34:27","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(S)"},
|
||||
{"type":"VARSCOPE","name":"t.cell1.d","addr":"(KB)","loc":"d,35:30,35:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(T)"},
|
||||
{"type":"VARSCOPE","name":"t.cell1.q","addr":"(LB)","loc":"d,36:30,36:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(U)"},
|
||||
{"type":"VARSCOPE","name":"t.cell1.IGNORED","addr":"(MB)","loc":"d,39:15,39:22","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(V)"},
|
||||
{"type":"VARSCOPE","name":"t.cell2.clk","addr":"(NB)","loc":"d,48:10,48:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(X)"},
|
||||
{"type":"VARSCOPE","name":"t.cell2.d","addr":"(OB)","loc":"d,49:16,49:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Y)"},
|
||||
{"type":"VARSCOPE","name":"t.cell2.q","addr":"(PB)","loc":"d,50:22,50:23","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Z)"}
|
||||
{"type":"ASSIGNW","name":"","addr":"(FB)","loc":"d,15:22,15:23","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"q","addr":"(GB)","loc":"d,15:22,15:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.q","addr":"(HB)","loc":"d,15:22,15:23","dtypep":"(H)","access":"WR","varp":"(L)","varScopep":"(EB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"t.clk","addr":"(IB)","loc":"d,13:10,13:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(M)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(JB)","loc":"d,13:10,13:13","dtypep":"(J)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"clk","addr":"(KB)","loc":"d,13:10,13:13","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.clk","addr":"(LB)","loc":"d,13:10,13:13","dtypep":"(J)","access":"WR","varp":"(M)","varScopep":"(IB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"t.d","addr":"(MB)","loc":"d,14:16,14:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(N)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(NB)","loc":"d,14:16,14:17","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"d","addr":"(OB)","loc":"d,14:16,14:17","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.d","addr":"(PB)","loc":"d,14:16,14:17","dtypep":"(H)","access":"WR","varp":"(N)","varScopep":"(MB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"t.between","addr":"(QB)","loc":"d,17:22,17:29","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(O)"},
|
||||
{"type":"VARSCOPE","name":"t.cell1.WIDTH","addr":"(RB)","loc":"d,32:15,32:20","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(P)"},
|
||||
{"type":"VARSCOPE","name":"t.cell1.clk","addr":"(SB)","loc":"d,34:24,34:27","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(S)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(TB)","loc":"d,34:24,34:27","dtypep":"(J)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"clk","addr":"(UB)","loc":"d,34:24,34:27","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell1.clk","addr":"(VB)","loc":"d,34:24,34:27","dtypep":"(J)","access":"WR","varp":"(S)","varScopep":"(SB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"t.cell1.d","addr":"(WB)","loc":"d,35:30,35:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(T)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(XB)","loc":"d,35:30,35:31","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"d","addr":"(YB)","loc":"d,35:30,35:31","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell1.d","addr":"(ZB)","loc":"d,35:30,35:31","dtypep":"(H)","access":"WR","varp":"(T)","varScopep":"(WB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"t.cell1.q","addr":"(AC)","loc":"d,36:30,36:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(U)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(BC)","loc":"d,36:30,36:31","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"t.between","addr":"(CC)","loc":"d,36:30,36:31","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(QB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell1.q","addr":"(DC)","loc":"d,36:30,36:31","dtypep":"(H)","access":"WR","varp":"(U)","varScopep":"(AC)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"t.cell1.IGNORED","addr":"(EC)","loc":"d,39:15,39:22","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(V)"},
|
||||
{"type":"VARSCOPE","name":"t.cell2.clk","addr":"(FC)","loc":"d,48:10,48:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(X)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(GC)","loc":"d,48:10,48:13","dtypep":"(J)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"clk","addr":"(HC)","loc":"d,48:10,48:13","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell2.clk","addr":"(IC)","loc":"d,48:10,48:13","dtypep":"(J)","access":"WR","varp":"(X)","varScopep":"(FC)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"t.cell2.d","addr":"(JC)","loc":"d,49:16,49:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Y)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(KC)","loc":"d,49:16,49:17","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"t.between","addr":"(LC)","loc":"d,49:16,49:17","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(QB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell2.d","addr":"(MC)","loc":"d,49:16,49:17","dtypep":"(H)","access":"WR","varp":"(Y)","varScopep":"(JC)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"t.cell2.q","addr":"(NC)","loc":"d,50:22,50:23","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Z)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(OC)","loc":"d,50:22,50:23","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"q","addr":"(PC)","loc":"d,50:22,50:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell2.q","addr":"(QC)","loc":"d,50:22,50:23","dtypep":"(H)","access":"WR","varp":"(Z)","varScopep":"(NC)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []}
|
||||
],
|
||||
"blocksp": [
|
||||
{"type":"ASSIGNW","name":"","addr":"(QB)","loc":"d,15:22,15:23","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"q","addr":"(RB)","loc":"d,15:22,15:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.q","addr":"(SB)","loc":"d,15:22,15:23","dtypep":"(H)","access":"WR","varp":"(L)","varScopep":"(EB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ASSIGNW","name":"","addr":"(TB)","loc":"d,13:10,13:13","dtypep":"(J)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"clk","addr":"(UB)","loc":"d,13:10,13:13","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.clk","addr":"(VB)","loc":"d,13:10,13:13","dtypep":"(J)","access":"WR","varp":"(M)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ASSIGNW","name":"","addr":"(WB)","loc":"d,14:16,14:17","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"d","addr":"(XB)","loc":"d,14:16,14:17","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.d","addr":"(YB)","loc":"d,14:16,14:17","dtypep":"(H)","access":"WR","varp":"(N)","varScopep":"(GB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ASSIGNW","name":"","addr":"(ZB)","loc":"d,36:30,36:31","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"t.between","addr":"(AC)","loc":"d,20:14,20:21","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(HB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell1.q","addr":"(BC)","loc":"d,36:30,36:31","dtypep":"(H)","access":"WR","varp":"(U)","varScopep":"(LB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ASSIGNW","name":"","addr":"(CC)","loc":"d,34:24,34:27","dtypep":"(J)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"t.clk","addr":"(DC)","loc":"d,21:42,21:45","dtypep":"(J)","access":"RD","varp":"(M)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell1.clk","addr":"(EC)","loc":"d,34:24,34:27","dtypep":"(J)","access":"WR","varp":"(S)","varScopep":"(JB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ASSIGNW","name":"","addr":"(FC)","loc":"d,35:30,35:31","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"t.d","addr":"(GC)","loc":"d,22:42,22:43","dtypep":"(H)","access":"RD","varp":"(N)","varScopep":"(GB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell1.d","addr":"(HC)","loc":"d,35:30,35:31","dtypep":"(H)","access":"WR","varp":"(T)","varScopep":"(KB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ALWAYS","name":"","addr":"(IC)","loc":"d,41:4,41:10","keyword":"always","isSuspendable":false,"needProcess":false,
|
||||
{"type":"ALWAYS","name":"","addr":"(RC)","loc":"d,41:4,41:10","keyword":"always","isSuspendable":false,"needProcess":false,
|
||||
"sentreep": [
|
||||
{"type":"SENTREE","name":"","addr":"(JC)","loc":"d,41:11,41:12","isMulti":false,
|
||||
{"type":"SENTREE","name":"","addr":"(SC)","loc":"d,41:11,41:12","isMulti":false,
|
||||
"sensesp": [
|
||||
{"type":"SENITEM","name":"","addr":"(KC)","loc":"d,41:13,41:20","edgeType":"POS",
|
||||
{"type":"SENITEM","name":"","addr":"(TC)","loc":"d,41:13,41:20","edgeType":"POS",
|
||||
"sensp": [
|
||||
{"type":"VARREF","name":"clk","addr":"(LC)","loc":"d,41:21,41:24","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"clk","addr":"(UC)","loc":"d,41:21,41:24","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
|
||||
],"condp": []}
|
||||
]}
|
||||
],
|
||||
"stmtsp": [
|
||||
{"type":"ASSIGNDLY","name":"","addr":"(MC)","loc":"d,42:8,42:10","dtypep":"(H)",
|
||||
{"type":"ASSIGNDLY","name":"","addr":"(VC)","loc":"d,42:8,42:10","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"d","addr":"(NC)","loc":"d,42:11,42:12","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"d","addr":"(WC)","loc":"d,42:11,42:12","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.between","addr":"(OC)","loc":"d,42:6,42:7","dtypep":"(H)","access":"WR","varp":"(O)","varScopep":"(HB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"t.between","addr":"(XC)","loc":"d,42:6,42:7","dtypep":"(H)","access":"WR","varp":"(O)","varScopep":"(QB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": []}
|
||||
]},
|
||||
{"type":"ASSIGNW","name":"","addr":"(PC)","loc":"d,49:16,49:17","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"t.between","addr":"(QC)","loc":"d,25:16,25:23","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(HB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell2.d","addr":"(RC)","loc":"d,49:16,49:17","dtypep":"(H)","access":"WR","varp":"(Y)","varScopep":"(OB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ASSIGNW","name":"","addr":"(SC)","loc":"d,50:22,50:23","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"t.q","addr":"(TC)","loc":"d,26:42,26:43","dtypep":"(H)","access":"RD","varp":"(L)","varScopep":"(EB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell2.q","addr":"(UC)","loc":"d,50:22,50:23","dtypep":"(H)","access":"WR","varp":"(Z)","varScopep":"(PB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ASSIGNW","name":"","addr":"(VC)","loc":"d,48:10,48:13","dtypep":"(J)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"t.clk","addr":"(WC)","loc":"d,27:42,27:45","dtypep":"(J)","access":"RD","varp":"(M)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"t.cell2.clk","addr":"(XC)","loc":"d,48:10,48:13","dtypep":"(J)","access":"WR","varp":"(X)","varScopep":"(NB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ASSIGNW","name":"","addr":"(YC)","loc":"d,53:13,53:14","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"t.between","addr":"(ZC)","loc":"d,17:22,17:29","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(HB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"t.between","addr":"(ZC)","loc":"d,17:22,17:29","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(QB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"q","addr":"(AD)","loc":"d,53:13,53:14","dtypep":"(H)","access":"WR","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
|
||||
|
|
|
|||
|
|
@ -11,24 +11,22 @@
|
|||
"varsp": [
|
||||
{"type":"VARSCOPE","name":"i_clk","addr":"(L)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(G)"},
|
||||
{"type":"VARSCOPE","name":"top.i_clk","addr":"(M)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(I)"},
|
||||
{"type":"VARSCOPE","name":"top.f.i_clk","addr":"(N)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"}
|
||||
],
|
||||
"blocksp": [
|
||||
{"type":"ASSIGNW","name":"","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)",
|
||||
{"type":"ASSIGNW","name":"","addr":"(N)","loc":"d,11:24,11:29","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"i_clk","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"top.i_clk","addr":"(Q)","loc":"d,11:24,11:29","dtypep":"(H)","access":"WR","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"top.i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(H)","access":"WR","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"top.f.i_clk","addr":"(Q)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"top.i_clk","addr":"(S)","loc":"d,12:7,12:8","dtypep":"(H)","access":"RD","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"i_clk","addr":"(S)","loc":"d,7:24,7:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"top.f.i_clk","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)","access":"WR","varp":"(J)","varScopep":"(N)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"top.f.i_clk","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)","access":"WR","varp":"(J)","varScopep":"(Q)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []}
|
||||
],"inlinesp": []}
|
||||
],"blocksp": [],"inlinesp": []}
|
||||
]}
|
||||
]}
|
||||
],"filesp": [],
|
||||
|
|
|
|||
|
|
@ -11,24 +11,22 @@
|
|||
"varsp": [
|
||||
{"type":"VARSCOPE","name":"i_clk","addr":"(L)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(G)"},
|
||||
{"type":"VARSCOPE","name":"top.i_clk","addr":"(M)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(I)"},
|
||||
{"type":"VARSCOPE","name":"top.f.i_clk","addr":"(N)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"}
|
||||
],
|
||||
"blocksp": [
|
||||
{"type":"ASSIGNW","name":"","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)",
|
||||
{"type":"ASSIGNW","name":"","addr":"(N)","loc":"d,11:24,11:29","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"i_clk","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"top.i_clk","addr":"(Q)","loc":"d,11:24,11:29","dtypep":"(H)","access":"WR","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"top.i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(H)","access":"WR","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"top.f.i_clk","addr":"(Q)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"top.i_clk","addr":"(S)","loc":"d,12:7,12:8","dtypep":"(H)","access":"RD","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"i_clk","addr":"(S)","loc":"d,7:24,7:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"top.f.i_clk","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)","access":"WR","varp":"(J)","varScopep":"(N)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"top.f.i_clk","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)","access":"WR","varp":"(J)","varScopep":"(Q)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []}
|
||||
],"inlinesp": []}
|
||||
],"blocksp": [],"inlinesp": []}
|
||||
]}
|
||||
]}
|
||||
],"filesp": [],
|
||||
|
|
|
|||
|
|
@ -19,47 +19,47 @@
|
|||
{"type":"VARSCOPE","name":"o_a","addr":"(T)","loc":"d,11:25,11:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(J)"},
|
||||
{"type":"VARSCOPE","name":"o_b","addr":"(U)","loc":"d,12:25,12:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(L)"},
|
||||
{"type":"VARSCOPE","name":"vlvbound_test.i_a","addr":"(V)","loc":"d,9:25,9:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(M)"},
|
||||
{"type":"VARSCOPE","name":"vlvbound_test.i_b","addr":"(W)","loc":"d,10:25,10:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(N)"},
|
||||
{"type":"VARSCOPE","name":"vlvbound_test.o_a","addr":"(X)","loc":"d,11:25,11:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(O)"},
|
||||
{"type":"VARSCOPE","name":"vlvbound_test.o_b","addr":"(Y)","loc":"d,12:25,12:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(P)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(Z)","loc":"d,15:34,15:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(AB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(BB)","loc":"d,15:57,15:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(CB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(DB)","loc":"d,16:17,16:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(EB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(FB)","loc":"d,17:13,17:14","dtypep":"(GB)","isTrace":true,"scopep":"(Q)","varp":"(HB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(IB)","loc":"d,15:34,15:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(JB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(KB)","loc":"d,15:57,15:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(LB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(MB)","loc":"d,16:17,16:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(NB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(OB)","loc":"d,17:13,17:14","dtypep":"(GB)","isTrace":true,"scopep":"(Q)","varp":"(PB)"}
|
||||
{"type":"ASSIGNW","name":"","addr":"(W)","loc":"d,9:25,9:28","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"i_a","addr":"(X)","loc":"d,9:25,9:28","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(R)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"vlvbound_test.i_a","addr":"(Y)","loc":"d,9:25,9:28","dtypep":"(H)","access":"WR","varp":"(M)","varScopep":"(V)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"vlvbound_test.i_b","addr":"(Z)","loc":"d,10:25,10:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(N)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(AB)","loc":"d,10:25,10:28","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"i_b","addr":"(BB)","loc":"d,10:25,10:28","dtypep":"(H)","access":"RD","varp":"(I)","varScopep":"(S)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"vlvbound_test.i_b","addr":"(CB)","loc":"d,10:25,10:28","dtypep":"(H)","access":"WR","varp":"(N)","varScopep":"(Z)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"vlvbound_test.o_a","addr":"(DB)","loc":"d,11:25,11:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(O)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(EB)","loc":"d,11:25,11:28","dtypep":"(K)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"o_a","addr":"(FB)","loc":"d,11:25,11:28","dtypep":"(K)","access":"RD","varp":"(J)","varScopep":"(T)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"vlvbound_test.o_a","addr":"(GB)","loc":"d,11:25,11:28","dtypep":"(K)","access":"WR","varp":"(O)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"vlvbound_test.o_b","addr":"(HB)","loc":"d,12:25,12:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(P)"},
|
||||
{"type":"ASSIGNW","name":"","addr":"(IB)","loc":"d,12:25,12:28","dtypep":"(K)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"o_b","addr":"(JB)","loc":"d,12:25,12:28","dtypep":"(K)","access":"RD","varp":"(L)","varScopep":"(U)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"vlvbound_test.o_b","addr":"(KB)","loc":"d,12:25,12:28","dtypep":"(K)","access":"WR","varp":"(P)","varScopep":"(HB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(LB)","loc":"d,15:34,15:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(MB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(NB)","loc":"d,15:57,15:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(OB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(PB)","loc":"d,16:17,16:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(QB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(RB)","loc":"d,17:13,17:14","dtypep":"(SB)","isTrace":true,"scopep":"(Q)","varp":"(TB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(UB)","loc":"d,15:34,15:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(VB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(WB)","loc":"d,15:57,15:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(XB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(YB)","loc":"d,16:17,16:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(ZB)"},
|
||||
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(AC)","loc":"d,17:13,17:14","dtypep":"(SB)","isTrace":true,"scopep":"(Q)","varp":"(BC)"}
|
||||
],
|
||||
"blocksp": [
|
||||
{"type":"ASSIGNW","name":"","addr":"(QB)","loc":"d,9:25,9:28","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"i_a","addr":"(RB)","loc":"d,9:25,9:28","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(R)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"vlvbound_test.i_a","addr":"(SB)","loc":"d,9:25,9:28","dtypep":"(H)","access":"WR","varp":"(M)","varScopep":"(V)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ASSIGNW","name":"","addr":"(TB)","loc":"d,10:25,10:28","dtypep":"(H)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"i_b","addr":"(UB)","loc":"d,10:25,10:28","dtypep":"(H)","access":"RD","varp":"(I)","varScopep":"(S)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"vlvbound_test.i_b","addr":"(VB)","loc":"d,10:25,10:28","dtypep":"(H)","access":"WR","varp":"(N)","varScopep":"(W)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ASSIGNW","name":"","addr":"(WB)","loc":"d,11:25,11:28","dtypep":"(K)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"o_a","addr":"(XB)","loc":"d,11:25,11:28","dtypep":"(K)","access":"RD","varp":"(J)","varScopep":"(T)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"vlvbound_test.o_a","addr":"(YB)","loc":"d,11:25,11:28","dtypep":"(K)","access":"WR","varp":"(O)","varScopep":"(X)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ASSIGNW","name":"","addr":"(ZB)","loc":"d,12:25,12:28","dtypep":"(K)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"o_b","addr":"(AC)","loc":"d,12:25,12:28","dtypep":"(K)","access":"RD","varp":"(L)","varScopep":"(U)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"vlvbound_test.o_b","addr":"(BC)","loc":"d,12:25,12:28","dtypep":"(K)","access":"WR","varp":"(P)","varScopep":"(Y)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": [],"strengthSpecp": []},
|
||||
{"type":"ALWAYS","name":"","addr":"(CC)","loc":"d,24:14,24:15","keyword":"always","isSuspendable":false,"needProcess":false,"sentreep": [],
|
||||
"stmtsp": [
|
||||
{"type":"COMMENT","name":"Function: foo","addr":"(DC)","loc":"d,24:16,24:19"},
|
||||
|
|
@ -68,22 +68,22 @@
|
|||
{"type":"VARREF","name":"i_a","addr":"(FC)","loc":"d,24:20,24:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(R)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(GC)","loc":"d,15:57,15:60","dtypep":"(H)","access":"WR","varp":"(CB)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(GC)","loc":"d,15:57,15:60","dtypep":"(H)","access":"WR","varp":"(OB)","varScopep":"(NB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": []},
|
||||
{"type":"CRESET","name":"","addr":"(HC)","loc":"d,16:17,16:20","constructing":false,
|
||||
"varrefp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(IC)","loc":"d,16:17,16:20","dtypep":"(K)","access":"WR","varp":"(EB)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(IC)","loc":"d,16:17,16:20","dtypep":"(K)","access":"WR","varp":"(QB)","varScopep":"(PB)","classOrPackagep":"UNLINKED"}
|
||||
]},
|
||||
{"type":"CRESET","name":"","addr":"(JC)","loc":"d,17:13,17:14","constructing":false,
|
||||
"varrefp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(KC)","loc":"d,17:13,17:14","dtypep":"(GB)","access":"WR","varp":"(HB)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(KC)","loc":"d,17:13,17:14","dtypep":"(SB)","access":"WR","varp":"(TB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"}
|
||||
]},
|
||||
{"type":"ASSIGN","name":"","addr":"(LC)","loc":"d,18:11,18:12","dtypep":"(GB)",
|
||||
{"type":"ASSIGN","name":"","addr":"(LC)","loc":"d,18:11,18:12","dtypep":"(SB)",
|
||||
"rhsp": [
|
||||
{"type":"CONST","name":"32'sh0","addr":"(MC)","loc":"d,18:12,18:13","dtypep":"(NC)"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(OC)","loc":"d,18:10,18:11","dtypep":"(GB)","access":"WR","varp":"(HB)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(OC)","loc":"d,18:10,18:11","dtypep":"(SB)","access":"WR","varp":"(TB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": []},
|
||||
{"type":"WHILE","name":"","addr":"(PC)","loc":"d,18:5,18:8",
|
||||
"condp": [
|
||||
|
|
@ -92,7 +92,7 @@
|
|||
{"type":"CONST","name":"32'sh7","addr":"(SC)","loc":"d,18:20,18:21","dtypep":"(NC)"}
|
||||
],
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(TC)","loc":"d,18:16,18:17","dtypep":"(GB)","access":"RD","varp":"(HB)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(TC)","loc":"d,18:16,18:17","dtypep":"(SB)","access":"RD","varp":"(TB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"}
|
||||
]}
|
||||
],
|
||||
"stmtsp": [
|
||||
|
|
@ -105,7 +105,7 @@
|
|||
"rhsp": [
|
||||
{"type":"SEL","name":"","addr":"(YC)","loc":"d,19:20,19:21","dtypep":"(XC)","widthConst":2,"declRange":"[15:0]","declElWidth":1,
|
||||
"fromp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(ZC)","loc":"d,19:17,19:20","dtypep":"(H)","access":"RD","varp":"(CB)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(ZC)","loc":"d,19:17,19:20","dtypep":"(H)","access":"RD","varp":"(OB)","varScopep":"(NB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lsbp": [
|
||||
{"type":"SEL","name":"","addr":"(AD)","loc":"d,19:22,19:23","dtypep":"(BD)","widthConst":4,
|
||||
|
|
@ -115,7 +115,7 @@
|
|||
{"type":"CONST","name":"32'sh2","addr":"(DD)","loc":"d,19:23,19:24","dtypep":"(NC)"}
|
||||
],
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(ED)","loc":"d,19:21,19:22","dtypep":"(GB)","access":"RD","varp":"(HB)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(ED)","loc":"d,19:21,19:22","dtypep":"(SB)","access":"RD","varp":"(TB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"}
|
||||
]}
|
||||
],
|
||||
"lsbp": [
|
||||
|
|
@ -127,12 +127,12 @@
|
|||
"lhsp": [
|
||||
{"type":"SEL","name":"","addr":"(HD)","loc":"d,19:10,19:11","dtypep":"(RC)","widthConst":1,"declRange":"[6:0]","declElWidth":1,
|
||||
"fromp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(ID)","loc":"d,19:7,19:10","dtypep":"(K)","access":"WR","varp":"(EB)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(ID)","loc":"d,19:7,19:10","dtypep":"(K)","access":"WR","varp":"(QB)","varScopep":"(PB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lsbp": [
|
||||
{"type":"SEL","name":"","addr":"(JD)","loc":"d,19:11,19:12","dtypep":"(KD)","widthConst":3,
|
||||
"fromp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(LD)","loc":"d,19:11,19:12","dtypep":"(GB)","access":"RD","varp":"(HB)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(LD)","loc":"d,19:11,19:12","dtypep":"(SB)","access":"RD","varp":"(TB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lsbp": [
|
||||
{"type":"CONST","name":"32'h0","addr":"(MD)","loc":"d,19:11,19:12","dtypep":"(GD)"}
|
||||
|
|
@ -141,30 +141,30 @@
|
|||
],"timingControlp": []}
|
||||
],
|
||||
"incsp": [
|
||||
{"type":"ASSIGN","name":"","addr":"(ND)","loc":"d,18:24,18:26","dtypep":"(GB)",
|
||||
{"type":"ASSIGN","name":"","addr":"(ND)","loc":"d,18:24,18:26","dtypep":"(SB)",
|
||||
"rhsp": [
|
||||
{"type":"ADD","name":"","addr":"(OD)","loc":"d,18:24,18:26","dtypep":"(GD)",
|
||||
"lhsp": [
|
||||
{"type":"CONST","name":"32'h1","addr":"(PD)","loc":"d,18:24,18:26","dtypep":"(GD)"}
|
||||
],
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(QD)","loc":"d,18:23,18:24","dtypep":"(GB)","access":"RD","varp":"(HB)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(QD)","loc":"d,18:23,18:24","dtypep":"(SB)","access":"RD","varp":"(TB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"}
|
||||
]}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(RD)","loc":"d,18:23,18:24","dtypep":"(GB)","access":"WR","varp":"(HB)","varScopep":"(FB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(RD)","loc":"d,18:23,18:24","dtypep":"(SB)","access":"WR","varp":"(TB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": []}
|
||||
]},
|
||||
{"type":"ASSIGN","name":"","addr":"(SD)","loc":"d,21:5,21:11","dtypep":"(K)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(TD)","loc":"d,21:12,21:15","dtypep":"(K)","access":"RD","varp":"(EB)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(TD)","loc":"d,21:12,21:15","dtypep":"(K)","access":"RD","varp":"(QB)","varScopep":"(PB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(UD)","loc":"d,21:5,21:11","dtypep":"(K)","access":"WR","varp":"(AB)","varScopep":"(Z)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(UD)","loc":"d,21:5,21:11","dtypep":"(K)","access":"WR","varp":"(MB)","varScopep":"(LB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": []},
|
||||
{"type":"ASSIGN","name":"","addr":"(VD)","loc":"d,24:14,24:15","dtypep":"(K)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(WD)","loc":"d,24:16,24:19","dtypep":"(K)","access":"RD","varp":"(AB)","varScopep":"(Z)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(WD)","loc":"d,24:16,24:19","dtypep":"(K)","access":"RD","varp":"(MB)","varScopep":"(LB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"o_a","addr":"(XD)","loc":"d,24:10,24:13","dtypep":"(K)","access":"WR","varp":"(J)","varScopep":"(T)","classOrPackagep":"UNLINKED"}
|
||||
|
|
@ -178,22 +178,22 @@
|
|||
{"type":"VARREF","name":"i_b","addr":"(BE)","loc":"d,25:20,25:23","dtypep":"(H)","access":"RD","varp":"(I)","varScopep":"(S)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(CE)","loc":"d,15:57,15:60","dtypep":"(H)","access":"WR","varp":"(LB)","varScopep":"(KB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(CE)","loc":"d,15:57,15:60","dtypep":"(H)","access":"WR","varp":"(XB)","varScopep":"(WB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": []},
|
||||
{"type":"CRESET","name":"","addr":"(DE)","loc":"d,16:17,16:20","constructing":false,
|
||||
"varrefp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(EE)","loc":"d,16:17,16:20","dtypep":"(K)","access":"WR","varp":"(NB)","varScopep":"(MB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(EE)","loc":"d,16:17,16:20","dtypep":"(K)","access":"WR","varp":"(ZB)","varScopep":"(YB)","classOrPackagep":"UNLINKED"}
|
||||
]},
|
||||
{"type":"CRESET","name":"","addr":"(FE)","loc":"d,17:13,17:14","constructing":false,
|
||||
"varrefp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(GE)","loc":"d,17:13,17:14","dtypep":"(GB)","access":"WR","varp":"(PB)","varScopep":"(OB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(GE)","loc":"d,17:13,17:14","dtypep":"(SB)","access":"WR","varp":"(BC)","varScopep":"(AC)","classOrPackagep":"UNLINKED"}
|
||||
]},
|
||||
{"type":"ASSIGN","name":"","addr":"(HE)","loc":"d,18:11,18:12","dtypep":"(GB)",
|
||||
{"type":"ASSIGN","name":"","addr":"(HE)","loc":"d,18:11,18:12","dtypep":"(SB)",
|
||||
"rhsp": [
|
||||
{"type":"CONST","name":"32'sh0","addr":"(IE)","loc":"d,18:12,18:13","dtypep":"(NC)"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(JE)","loc":"d,18:10,18:11","dtypep":"(GB)","access":"WR","varp":"(PB)","varScopep":"(OB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(JE)","loc":"d,18:10,18:11","dtypep":"(SB)","access":"WR","varp":"(BC)","varScopep":"(AC)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": []},
|
||||
{"type":"WHILE","name":"","addr":"(KE)","loc":"d,18:5,18:8",
|
||||
"condp": [
|
||||
|
|
@ -202,7 +202,7 @@
|
|||
{"type":"CONST","name":"32'sh7","addr":"(ME)","loc":"d,18:20,18:21","dtypep":"(NC)"}
|
||||
],
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(NE)","loc":"d,18:16,18:17","dtypep":"(GB)","access":"RD","varp":"(PB)","varScopep":"(OB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(NE)","loc":"d,18:16,18:17","dtypep":"(SB)","access":"RD","varp":"(BC)","varScopep":"(AC)","classOrPackagep":"UNLINKED"}
|
||||
]}
|
||||
],
|
||||
"stmtsp": [
|
||||
|
|
@ -215,7 +215,7 @@
|
|||
"rhsp": [
|
||||
{"type":"SEL","name":"","addr":"(RE)","loc":"d,19:20,19:21","dtypep":"(XC)","widthConst":2,"declRange":"[15:0]","declElWidth":1,
|
||||
"fromp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(SE)","loc":"d,19:17,19:20","dtypep":"(H)","access":"RD","varp":"(LB)","varScopep":"(KB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(SE)","loc":"d,19:17,19:20","dtypep":"(H)","access":"RD","varp":"(XB)","varScopep":"(WB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lsbp": [
|
||||
{"type":"SEL","name":"","addr":"(TE)","loc":"d,19:22,19:23","dtypep":"(BD)","widthConst":4,
|
||||
|
|
@ -225,7 +225,7 @@
|
|||
{"type":"CONST","name":"32'sh2","addr":"(VE)","loc":"d,19:23,19:24","dtypep":"(NC)"}
|
||||
],
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(WE)","loc":"d,19:21,19:22","dtypep":"(GB)","access":"RD","varp":"(PB)","varScopep":"(OB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(WE)","loc":"d,19:21,19:22","dtypep":"(SB)","access":"RD","varp":"(BC)","varScopep":"(AC)","classOrPackagep":"UNLINKED"}
|
||||
]}
|
||||
],
|
||||
"lsbp": [
|
||||
|
|
@ -237,12 +237,12 @@
|
|||
"lhsp": [
|
||||
{"type":"SEL","name":"","addr":"(YE)","loc":"d,19:10,19:11","dtypep":"(RC)","widthConst":1,"declRange":"[6:0]","declElWidth":1,
|
||||
"fromp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(ZE)","loc":"d,19:7,19:10","dtypep":"(K)","access":"WR","varp":"(NB)","varScopep":"(MB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(ZE)","loc":"d,19:7,19:10","dtypep":"(K)","access":"WR","varp":"(ZB)","varScopep":"(YB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lsbp": [
|
||||
{"type":"SEL","name":"","addr":"(AF)","loc":"d,19:11,19:12","dtypep":"(KD)","widthConst":3,
|
||||
"fromp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(BF)","loc":"d,19:11,19:12","dtypep":"(GB)","access":"RD","varp":"(PB)","varScopep":"(OB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(BF)","loc":"d,19:11,19:12","dtypep":"(SB)","access":"RD","varp":"(BC)","varScopep":"(AC)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lsbp": [
|
||||
{"type":"CONST","name":"32'h0","addr":"(CF)","loc":"d,19:11,19:12","dtypep":"(GD)"}
|
||||
|
|
@ -251,30 +251,30 @@
|
|||
],"timingControlp": []}
|
||||
],
|
||||
"incsp": [
|
||||
{"type":"ASSIGN","name":"","addr":"(DF)","loc":"d,18:24,18:26","dtypep":"(GB)",
|
||||
{"type":"ASSIGN","name":"","addr":"(DF)","loc":"d,18:24,18:26","dtypep":"(SB)",
|
||||
"rhsp": [
|
||||
{"type":"ADD","name":"","addr":"(EF)","loc":"d,18:24,18:26","dtypep":"(GD)",
|
||||
"lhsp": [
|
||||
{"type":"CONST","name":"32'h1","addr":"(FF)","loc":"d,18:24,18:26","dtypep":"(GD)"}
|
||||
],
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(GF)","loc":"d,18:23,18:24","dtypep":"(GB)","access":"RD","varp":"(PB)","varScopep":"(OB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(GF)","loc":"d,18:23,18:24","dtypep":"(SB)","access":"RD","varp":"(BC)","varScopep":"(AC)","classOrPackagep":"UNLINKED"}
|
||||
]}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(HF)","loc":"d,18:23,18:24","dtypep":"(GB)","access":"WR","varp":"(PB)","varScopep":"(OB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(HF)","loc":"d,18:23,18:24","dtypep":"(SB)","access":"WR","varp":"(BC)","varScopep":"(AC)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": []}
|
||||
]},
|
||||
{"type":"ASSIGN","name":"","addr":"(IF)","loc":"d,21:5,21:11","dtypep":"(K)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(JF)","loc":"d,21:12,21:15","dtypep":"(K)","access":"RD","varp":"(NB)","varScopep":"(MB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(JF)","loc":"d,21:12,21:15","dtypep":"(K)","access":"RD","varp":"(ZB)","varScopep":"(YB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(KF)","loc":"d,21:5,21:11","dtypep":"(K)","access":"WR","varp":"(JB)","varScopep":"(IB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(KF)","loc":"d,21:5,21:11","dtypep":"(K)","access":"WR","varp":"(VB)","varScopep":"(UB)","classOrPackagep":"UNLINKED"}
|
||||
],"timingControlp": []},
|
||||
{"type":"ASSIGN","name":"","addr":"(LF)","loc":"d,25:14,25:15","dtypep":"(K)",
|
||||
"rhsp": [
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(MF)","loc":"d,25:16,25:19","dtypep":"(K)","access":"RD","varp":"(JB)","varScopep":"(IB)","classOrPackagep":"UNLINKED"}
|
||||
{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(MF)","loc":"d,25:16,25:19","dtypep":"(K)","access":"RD","varp":"(VB)","varScopep":"(UB)","classOrPackagep":"UNLINKED"}
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"VARREF","name":"o_b","addr":"(NF)","loc":"d,25:10,25:13","dtypep":"(K)","access":"WR","varp":"(L)","varScopep":"(U)","classOrPackagep":"UNLINKED"}
|
||||
|
|
@ -282,14 +282,14 @@
|
|||
]}
|
||||
],"inlinesp": []}
|
||||
]},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(AB)","loc":"d,15:34,15:37","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__Vfuncout","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(CB)","loc":"d,15:57,15:60","dtypep":"(H)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__val","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(EB)","loc":"d,16:17,16:20","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__ret","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(HB)","loc":"d,17:13,17:14","dtypep":"(GB)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__i","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(JB)","loc":"d,15:34,15:37","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__Vfuncout","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(LB)","loc":"d,15:57,15:60","dtypep":"(H)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__val","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(NB)","loc":"d,16:17,16:20","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__ret","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(PB)","loc":"d,17:13,17:14","dtypep":"(GB)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__i","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(MB)","loc":"d,15:34,15:37","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__Vfuncout","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(OB)","loc":"d,15:57,15:60","dtypep":"(H)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__val","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(QB)","loc":"d,16:17,16:20","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__ret","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(TB)","loc":"d,17:13,17:14","dtypep":"(SB)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__i","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(VB)","loc":"d,15:34,15:37","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__Vfuncout","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(XB)","loc":"d,15:57,15:60","dtypep":"(H)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__val","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(ZB)","loc":"d,16:17,16:20","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__ret","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
|
||||
{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(BC)","loc":"d,17:13,17:14","dtypep":"(SB)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__i","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
|
||||
]}
|
||||
],"filesp": [],
|
||||
"miscsp": [
|
||||
|
|
@ -299,7 +299,7 @@
|
|||
{"type":"BASICDTYPE","name":"logic","addr":"(XC)","loc":"d,19:34,19:39","dtypep":"(XC)","keyword":"logic","range":"1:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,9:11,9:16","dtypep":"(H)","keyword":"logic","range":"15:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(K)","loc":"d,11:12,11:17","dtypep":"(K)","keyword":"logic","range":"6:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"integer","addr":"(GB)","loc":"d,17:5,17:12","dtypep":"(GB)","keyword":"integer","range":"31:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"integer","addr":"(SB)","loc":"d,17:5,17:12","dtypep":"(SB)","keyword":"integer","range":"31:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(KD)","loc":"d,19:10,19:11","dtypep":"(KD)","keyword":"logic","range":"2:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(GD)","loc":"d,19:11,19:12","dtypep":"(GD)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(BD)","loc":"d,19:20,19:21","dtypep":"(BD)","keyword":"logic","range":"3:0","generic":true,"rangep": []},
|
||||
|
|
|
|||
|
|
@ -40,41 +40,53 @@
|
|||
<varscope loc="d,13,10,13,13" name="clk" dtype_id="2"/>
|
||||
<varscope loc="d,14,16,14,17" name="d" dtype_id="1"/>
|
||||
<varscope loc="d,15,22,15,23" name="t.q" dtype_id="1"/>
|
||||
<varscope loc="d,13,10,13,13" name="t.clk" dtype_id="2"/>
|
||||
<varscope loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
|
||||
<varscope loc="d,17,22,17,29" name="t.between" dtype_id="1"/>
|
||||
<varscope loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3"/>
|
||||
<varscope loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
|
||||
<varscope loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
|
||||
<varscope loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
|
||||
<varscope loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3"/>
|
||||
<varscope loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
|
||||
<varscope loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
|
||||
<varscope loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
|
||||
<contassign loc="d,15,22,15,23" dtype_id="1">
|
||||
<varref loc="d,15,22,15,23" name="q" dtype_id="1"/>
|
||||
<varref loc="d,15,22,15,23" name="t.q" dtype_id="1"/>
|
||||
</contassign>
|
||||
<varscope loc="d,13,10,13,13" name="t.clk" dtype_id="2"/>
|
||||
<contassign loc="d,13,10,13,13" dtype_id="2">
|
||||
<varref loc="d,13,10,13,13" name="clk" dtype_id="2"/>
|
||||
<varref loc="d,13,10,13,13" name="t.clk" dtype_id="2"/>
|
||||
</contassign>
|
||||
<varscope loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
|
||||
<contassign loc="d,14,16,14,17" dtype_id="1">
|
||||
<varref loc="d,14,16,14,17" name="d" dtype_id="1"/>
|
||||
<varref loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
|
||||
</contassign>
|
||||
<contassign loc="d,36,30,36,31" dtype_id="1">
|
||||
<varref loc="d,20,14,20,21" name="t.between" dtype_id="1"/>
|
||||
<varref loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
|
||||
</contassign>
|
||||
<varscope loc="d,17,22,17,29" name="t.between" dtype_id="1"/>
|
||||
<varscope loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3"/>
|
||||
<varscope loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
|
||||
<contassign loc="d,34,24,34,27" dtype_id="2">
|
||||
<varref loc="d,21,42,21,45" name="t.clk" dtype_id="2"/>
|
||||
<varref loc="d,34,24,34,27" name="clk" dtype_id="2"/>
|
||||
<varref loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
|
||||
</contassign>
|
||||
<varscope loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
|
||||
<contassign loc="d,35,30,35,31" dtype_id="1">
|
||||
<varref loc="d,22,42,22,43" name="t.d" dtype_id="1"/>
|
||||
<varref loc="d,35,30,35,31" name="d" dtype_id="1"/>
|
||||
<varref loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
|
||||
</contassign>
|
||||
<varscope loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
|
||||
<contassign loc="d,36,30,36,31" dtype_id="1">
|
||||
<varref loc="d,36,30,36,31" name="t.between" dtype_id="1"/>
|
||||
<varref loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
|
||||
</contassign>
|
||||
<varscope loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3"/>
|
||||
<varscope loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
|
||||
<contassign loc="d,48,10,48,13" dtype_id="2">
|
||||
<varref loc="d,48,10,48,13" name="clk" dtype_id="2"/>
|
||||
<varref loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
|
||||
</contassign>
|
||||
<varscope loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
|
||||
<contassign loc="d,49,16,49,17" dtype_id="1">
|
||||
<varref loc="d,49,16,49,17" name="t.between" dtype_id="1"/>
|
||||
<varref loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
|
||||
</contassign>
|
||||
<varscope loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
|
||||
<contassign loc="d,50,22,50,23" dtype_id="1">
|
||||
<varref loc="d,50,22,50,23" name="q" dtype_id="1"/>
|
||||
<varref loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
|
||||
</contassign>
|
||||
<always loc="d,41,4,41,10">
|
||||
<sentree loc="d,41,11,41,12">
|
||||
<senitem loc="d,41,13,41,20" edgeType="POS">
|
||||
|
|
@ -86,18 +98,6 @@
|
|||
<varref loc="d,42,6,42,7" name="t.between" dtype_id="1"/>
|
||||
</assigndly>
|
||||
</always>
|
||||
<contassign loc="d,49,16,49,17" dtype_id="1">
|
||||
<varref loc="d,25,16,25,23" name="t.between" dtype_id="1"/>
|
||||
<varref loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
|
||||
</contassign>
|
||||
<contassign loc="d,50,22,50,23" dtype_id="1">
|
||||
<varref loc="d,26,42,26,43" name="t.q" dtype_id="1"/>
|
||||
<varref loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
|
||||
</contassign>
|
||||
<contassign loc="d,48,10,48,13" dtype_id="2">
|
||||
<varref loc="d,27,42,27,45" name="t.clk" dtype_id="2"/>
|
||||
<varref loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
|
||||
</contassign>
|
||||
<contassign loc="d,53,13,53,14" dtype_id="1">
|
||||
<varref loc="d,17,22,17,29" name="t.between" dtype_id="1"/>
|
||||
<varref loc="d,53,13,53,14" name="q" dtype_id="1"/>
|
||||
|
|
|
|||
|
|
@ -22,13 +22,13 @@
|
|||
<scope loc="d,11,8,11,11" name="TOP">
|
||||
<varscope loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
|
||||
<varscope loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
|
||||
<varscope loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
|
||||
<contassign loc="d,11,24,11,29" dtype_id="1">
|
||||
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
|
||||
<varref loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
|
||||
</contassign>
|
||||
<varscope loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
|
||||
<contassign loc="d,7,24,7,29" dtype_id="1">
|
||||
<varref loc="d,12,7,12,8" name="top.i_clk" dtype_id="1"/>
|
||||
<varref loc="d,7,24,7,29" name="i_clk" dtype_id="1"/>
|
||||
<varref loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
|
||||
</contassign>
|
||||
</scope>
|
||||
|
|
|
|||
|
|
@ -22,13 +22,13 @@
|
|||
<scope loc="d,11,8,11,11" name="TOP">
|
||||
<varscope loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
|
||||
<varscope loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
|
||||
<varscope loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
|
||||
<contassign loc="d,11,24,11,29" dtype_id="1">
|
||||
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
|
||||
<varref loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
|
||||
</contassign>
|
||||
<varscope loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
|
||||
<contassign loc="d,7,24,7,29" dtype_id="1">
|
||||
<varref loc="d,12,7,12,8" name="top.i_clk" dtype_id="1"/>
|
||||
<varref loc="d,7,24,7,29" name="i_clk" dtype_id="1"/>
|
||||
<varref loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
|
||||
</contassign>
|
||||
</scope>
|
||||
|
|
|
|||
|
|
@ -30,9 +30,25 @@
|
|||
<varscope loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
|
||||
<varscope loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
|
||||
<varscope loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1"/>
|
||||
<contassign loc="d,9,25,9,28" dtype_id="1">
|
||||
<varref loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
|
||||
<varref loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1"/>
|
||||
</contassign>
|
||||
<varscope loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1"/>
|
||||
<contassign loc="d,10,25,10,28" dtype_id="1">
|
||||
<varref loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
|
||||
<varref loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1"/>
|
||||
</contassign>
|
||||
<varscope loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2"/>
|
||||
<contassign loc="d,11,25,11,28" dtype_id="2">
|
||||
<varref loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
|
||||
<varref loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2"/>
|
||||
</contassign>
|
||||
<varscope loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2"/>
|
||||
<contassign loc="d,12,25,12,28" dtype_id="2">
|
||||
<varref loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
|
||||
<varref loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2"/>
|
||||
</contassign>
|
||||
<varscope loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
|
||||
<varscope loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
|
||||
<varscope loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
|
||||
|
|
@ -41,22 +57,6 @@
|
|||
<varscope loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
|
||||
<varscope loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
|
||||
<varscope loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
|
||||
<contassign loc="d,9,25,9,28" dtype_id="1">
|
||||
<varref loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
|
||||
<varref loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1"/>
|
||||
</contassign>
|
||||
<contassign loc="d,10,25,10,28" dtype_id="1">
|
||||
<varref loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
|
||||
<varref loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1"/>
|
||||
</contassign>
|
||||
<contassign loc="d,11,25,11,28" dtype_id="2">
|
||||
<varref loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
|
||||
<varref loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2"/>
|
||||
</contassign>
|
||||
<contassign loc="d,12,25,12,28" dtype_id="2">
|
||||
<varref loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
|
||||
<varref loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2"/>
|
||||
</contassign>
|
||||
<always loc="d,24,14,24,15">
|
||||
<comment loc="d,24,16,24,19" name="Function: foo"/>
|
||||
<assign loc="d,24,20,24,23" dtype_id="1">
|
||||
|
|
|
|||
Loading…
Reference in New Issue