Fix error instead of warning on large concat, msg1768.
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@ -29,6 +29,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix dotted generated array error, bug1005. [Jeff Bush, Johan Bjork]
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**** Fix dotted generated array error, bug1005. [Jeff Bush, Johan Bjork]
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**** Fix error instead of warning on large concat, msg1768. [Paul Rolfe]
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* Verilator 3.878 2015-11-01
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* Verilator 3.878 2015-11-01
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@ -978,7 +978,7 @@ V3Number& V3Number::opRepl (const V3Number& lhs, const V3Number& rhs) { // rhs i
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V3Number& V3Number::opRepl (const V3Number& lhs, uint32_t rhsval) { // rhs is # of times to replicate
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V3Number& V3Number::opRepl (const V3Number& lhs, uint32_t rhsval) { // rhs is # of times to replicate
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// i op repl, L(i)*value(rhs) bit return
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// i op repl, L(i)*value(rhs) bit return
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setZero();
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setZero();
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if (rhsval>8192) m_fileline->v3fatal("More than a 8k bit replication is probably wrong: "<<rhsval);
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if (rhsval>8192) m_fileline->v3warn(WIDTHCONCAT,"More than a 8k bit replication is probably wrong: "<<rhsval);
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int obit = 0;
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int obit = 0;
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for (unsigned times=0; times<rhsval; times++) {
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for (unsigned times=0; times<rhsval; times++) {
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for(int bit=0; bit<lhs.width(); bit++) {
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for(int bit=0; bit<lhs.width(); bit++) {
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@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2004 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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@ -0,0 +1,19 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Wilson Snyder.
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module t (/*AUTOARG*/);
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wire [32767:0] a;
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initial begin
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// verilator lint_off WIDTHCONCAT
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a = {32768{1'b1}};
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// verilator lint_on WIDTHCONCAT
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if (a[32000] != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,20 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2004 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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v_flags2 => ["--lint-only"],
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fails=>1,
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expect=>
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'%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:\d+: More than a 8k bit replication is probably wrong: 32768
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%Warning-WIDTHCONCAT: Use .*
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%Error: Exiting due to.*',
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);
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ok(1);
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1;
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@ -0,0 +1,14 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Wilson Snyder.
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module t (/*AUTOARG*/);
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wire [32767:0] a = {32768{1'b1}};
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initial begin
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$stop;
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end
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endmodule
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