From ebad6cde36fc17004261b6e6c8abe0ab18dca024 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 8 Dec 2015 21:25:43 -0500
Subject: [PATCH] Fix error instead of warning on large concat, msg1768.

---
 Changes                              |  2 ++
 src/V3Number.cpp                     |  2 +-
 test_regress/t/t_concat_large.pl     | 18 ++++++++++++++++++
 test_regress/t/t_concat_large.v      | 19 +++++++++++++++++++
 test_regress/t/t_concat_large_bad.pl | 20 ++++++++++++++++++++
 test_regress/t/t_concat_large_bad.v  | 14 ++++++++++++++
 6 files changed, 74 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_concat_large.pl
 create mode 100644 test_regress/t/t_concat_large.v
 create mode 100755 test_regress/t/t_concat_large_bad.pl
 create mode 100644 test_regress/t/t_concat_large_bad.v

diff --git a/Changes b/Changes
index d6a5b1ba3..235c5687a 100644
--- a/Changes
+++ b/Changes
@@ -29,6 +29,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix dotted generated array error, bug1005. [Jeff Bush, Johan Bjork]
 
+****  Fix error instead of warning on large concat, msg1768. [Paul Rolfe]
+
 
 * Verilator 3.878 2015-11-01
 
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 8196083ce..a240ccf9d 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -978,7 +978,7 @@ V3Number& V3Number::opRepl (const V3Number& lhs, const V3Number& rhs) {	// rhs i
 V3Number& V3Number::opRepl (const V3Number& lhs, uint32_t rhsval) {	// rhs is # of times to replicate
     // i op repl, L(i)*value(rhs) bit return
     setZero();
-    if (rhsval>8192) m_fileline->v3fatal("More than a 8k bit replication is probably wrong: "<<rhsval);
+    if (rhsval>8192) m_fileline->v3warn(WIDTHCONCAT,"More than a 8k bit replication is probably wrong: "<<rhsval);
     int obit = 0;
     for (unsigned times=0; times<rhsval; times++) {
 	for(int bit=0; bit<lhs.width(); bit++) {
diff --git a/test_regress/t/t_concat_large.pl b/test_regress/t/t_concat_large.pl
new file mode 100755
index 000000000..30da50378
--- /dev/null
+++ b/test_regress/t/t_concat_large.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2004 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_concat_large.v b/test_regress/t/t_concat_large.v
new file mode 100644
index 000000000..ab2f17e33
--- /dev/null
+++ b/test_regress/t/t_concat_large.v
@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   wire [32767:0] a;
+
+   initial begin
+      // verilator lint_off WIDTHCONCAT
+      a = {32768{1'b1}};
+      // verilator lint_on WIDTHCONCAT
+      if (a[32000] != 1'b1) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
diff --git a/test_regress/t/t_concat_large_bad.pl b/test_regress/t/t_concat_large_bad.pl
new file mode 100755
index 000000000..5a848e0a2
--- /dev/null
+++ b/test_regress/t/t_concat_large_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2004 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    v_flags2 => ["--lint-only"],
+    fails=>1,
+    expect=>
+'%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:\d+: More than a 8k bit replication is probably wrong: 32768
+%Warning-WIDTHCONCAT: Use .*
+%Error: Exiting due to.*',
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_concat_large_bad.v b/test_regress/t/t_concat_large_bad.v
new file mode 100644
index 000000000..7f966fa32
--- /dev/null
+++ b/test_regress/t/t_concat_large_bad.v
@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   wire [32767:0] a = {32768{1'b1}};
+
+   initial begin
+      $stop;
+   end
+
+endmodule