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Internals: Make AstAssignW a procedural statement (#6280) (#6556) 

Initial idea was to remodel AssignW as Assign under Alway. Trying that
uncovered some issues, the most difficult of them was that a delay
attached to a continuous assignment behaves differently from a delay
attached to a blocking assignment statement, so we need to keep the
knowledge of which flavour an assignment was until V3Timing.

So instead of removing AstAssignW, we always wrap it in an AstAlways,
with a special `keyword()` type. This makes it into a proper procedural
statement, which is almost equivalent to AstAssign, except for the case
when they contain a delay. We still gain the benefits of #6280 and can
simplify some code. Every AstNodeStmt should now be under an
AstNodeProcedure - which we should rename to AstProcess, or an
AstNodeFTask). As a result, V3Table can now handle AssignW for free.
Also uncovered and fixed a bug in handling intra-assignment delays if
a function is present on the RHS of an AssignW.

There is more work to be done towards #6280, and potentially simplifying
AssignW handing, but this is the minimal change required to tick it off
the TODO list for #6280.
This commit is contained in:
Geza Lore 2025-10-14 10:05:19 +02:00 committed by GitHub
parent 958d096e7f
commit eb53bca6fd
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
55 changed files with 1540 additions and 1411 deletions
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5
src/V3Active.cpp
View File

@ -506,12 +506,15 @@ class ActiveVisitor final : public VNVisitor {
moveUnderSpecial<AstSenItem::Final>(nodep);
}
void visit(AstCoverToggle* nodep) override { moveUnderSpecial<AstSenItem::Combo>(nodep); }
void visit(AstAssignW* nodep) override { moveUnderSpecial<AstSenItem::Combo>(nodep); }
void visit(AstAlways* nodep) override {
if (!nodep->stmtsp()) { // Empty always. Remove it now.
VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
return;
}
if (nodep->keyword() == VAlwaysKwd::CONT_ASSIGN) {
moveUnderSpecial<AstSenItem::Combo>(nodep);
return;
}
visitSenItems(nodep);
visitAlways(nodep, nodep->sentreep(), nodep->keyword());
}

3
src/V3ActiveTop.cpp
View File

@ -131,9 +131,6 @@ class ActiveTopVisitor final : public VNVisitor {
void visit(AstNodeProcedure* nodep) override { // LCOV_EXCL_LINE
nodep->v3fatalSrc("Node should have been under ACTIVE");
}
void visit(AstAssignW* nodep) override { // LCOV_EXCL_LINE
nodep->v3fatalSrc("Node should have been under ACTIVE");
}
//--------------------
void visit(AstNodeExpr*) override {} // Accelerate
void visit(AstVarScope*) override {} // Accelerate

3
src/V3AssertPre.cpp
View File

@ -273,7 +273,8 @@ private:
// Assign the sampled expression to the clockvar (IEEE 1800-2023 14.13)
AstSampled* const sampledp = new AstSampled{flp, exprp->cloneTreePure(false)};
sampledp->dtypeFrom(exprp);
m_clockingp->addNextHere(new AstAssignW{flp, refp, sampledp});
AstAssignW* const ap = new AstAssignW{flp, refp, sampledp};
m_clockingp->addNextHere(new AstAlways{ap});
} else if (skewp->isZero()) {
// #0 means the var has to be sampled in Observed (IEEE 1800-2023 14.13)
AstAssign* const assignp = new AstAssign{flp, refp, exprp->cloneTreePure(false)};

5
src/V3AstAttr.h
View File

@ -84,7 +84,7 @@ inline std::ostream& operator<<(std::ostream& os, const VAccess& rhs) { return o
class VAlwaysKwd final {
public:
enum en : uint8_t { ALWAYS, ALWAYS_FF, ALWAYS_LATCH, ALWAYS_COMB };
enum en : uint8_t { ALWAYS, ALWAYS_FF, ALWAYS_LATCH, ALWAYS_COMB, CONT_ASSIGN };
enum en m_e;
VAlwaysKwd()
: m_e{ALWAYS} {}
@ -95,7 +95,8 @@ public:
: m_e(static_cast<en>(_e)) {} // Need () or GCC 4.8 false warning
constexpr operator en() const { return m_e; }
const char* ascii() const {
static const char* const names[] = {"always", "always_ff", "always_latch", "always_comb"};
static const char* const names[]
= {"always", "always_ff", "always_latch", "always_comb", "cont_assign"};
return names[m_e];
}
};

4
src/V3AstInlines.h
View File

@ -144,6 +144,10 @@ bool AstBasicDType::ascending() const {
bool AstActive::hasClocked() const { return m_sentreep->hasClocked(); }
bool AstActive::hasCombo() const { return m_sentreep->hasCombo(); }
AstAlways::AstAlways(AstAssignW* assignp)
: ASTGEN_SUPER_Always(assignp->fileline(), assignp)
, m_keyword{VAlwaysKwd::CONT_ASSIGN} {}
AstElabDisplay::AstElabDisplay(FileLine* fl, VDisplayType dispType, AstNodeExpr* exprsp)
: ASTGEN_SUPER_ElabDisplay(fl) {
addFmtp(new AstSFormatF{fl, AstSFormatF::NoFormat{}, exprsp});

1
src/V3AstNodeOther.h
View File

@ -2649,6 +2649,7 @@ public:
, m_keyword{keyword} {
this->sentreep(sentreep);
}
inline AstAlways(AstAssignW* assignp);
ASTGEN_MEMBERS_AstAlways;
//
void dump(std::ostream& str) const override;

1
src/V3AstNodeStmt.h
View File

@ -1278,7 +1278,6 @@ public:
});
}
AstDelay* getLhsNetDelay() const;
AstAlways* convertToAlways();
};
// === AstNodeBlock ===

19
src/V3AstNodes.cpp
View File

@ -3188,25 +3188,6 @@ static AstDelay* getLhsNetDelayRecurse(const AstNodeExpr* const nodep) {
return nullptr;
}
AstDelay* AstAssignW::getLhsNetDelay() const { return getLhsNetDelayRecurse(lhsp()); }
AstAlways* AstAssignW::convertToAlways() {
const bool hasTimingControl = isTimingControl();
AstNodeExpr* const lhs1p = lhsp()->unlinkFrBack();
AstNodeExpr* const rhs1p = rhsp()->unlinkFrBack();
AstNode* const controlp = timingControlp() ? timingControlp()->unlinkFrBack() : nullptr;
FileLine* const flp = fileline();
AstNode* bodysp = new AstAssign{flp, lhs1p, rhs1p, controlp};
if (hasTimingControl) {
// If there's a timing control, put the assignment in a fork..join_none. This process won't
// get marked as suspendable and thus will be scheduled normally
AstBegin* const beginp = new AstBegin{flp, "", bodysp, false};
AstFork* const forkp = new AstFork{flp, "", beginp};
forkp->joinType(VJoinType::JOIN_NONE);
bodysp = forkp;
}
AstAlways* const newp = new AstAlways{flp, VAlwaysKwd::ALWAYS, nullptr, bodysp};
replaceWith(newp); // User expected to then deleteTree();
return newp;
}
string AstCase::pragmaString() const {
if (fullPragma() && parallelPragma())

1
src/V3CfgBuilder.cpp
View File

@ -86,6 +86,7 @@ class CfgBuilder final : public VNVisitorConst {
// Representable non control-flow statements
void visit(AstAssign* nodep) override { simpleStatement(nodep, !nodep->timingControlp()); }
void visit(AstAssignW* nodep) override { simpleStatement(nodep, !nodep->timingControlp()); }
void visit(AstComment*) override {} // ignore entirely
void visit(AstDisplay* nodep) override { simpleStatement(nodep); }
void visit(AstFinish* nodep) override { simpleStatement(nodep); }

1
src/V3CfgLiveVariables.cpp
View File

@ -162,6 +162,7 @@ class CfgLiveVariables final : VNVisitorConst {
}
void visit(AstAssign* nodep) override { single(nodep); }
void visit(AstAssignW* nodep) override { single(nodep); }
void visit(AstDisplay* nodep) override { single(nodep); }
void visit(AstFinish* nodep) override { single(nodep); }
void visit(AstStmtExpr* nodep) override { single(nodep); }

16
src/V3Const.cpp
View File

@ -3250,9 +3250,11 @@ class ConstVisitor final : public VNVisitor {
void visit(AstAssignW* nodep) override {
iterateChildren(nodep);
if (m_doNConst && replaceNodeAssign(nodep)) return;
AstNodeVarRef* const varrefp = VN_CAST(
nodep->lhsp(),
VarRef); // Not VarXRef, as different refs may set different values to each hierarchy
// Process containing this AssignW as single body statement
AstAlways* const procp = VN_CAST(nodep->backp(), Always);
if (!procp || procp->stmtsp() != nodep || nodep->nextp()) return;
// Not VarXRef, as different refs may set different values to each hierarchy
AstNodeVarRef* const varrefp = VN_CAST(nodep->lhsp(), VarRef);
if (m_wremove && !m_params && m_doNConst && m_modp && operandConst(nodep->rhsp())
&& !VN_AS(nodep->rhsp(), Const)->num().isFourState()
&& varrefp // Don't do messes with BITREFs/ARRAYREFs
@ -3266,10 +3268,10 @@ class ConstVisitor final : public VNVisitor {
// Make a initial assignment
AstNodeExpr* const exprp = nodep->rhsp()->unlinkFrBack();
varrefp->unlinkFrBack();
AstInitial* const newinitp = new AstInitial{
nodep->fileline(), new AstAssign{nodep->fileline(), varrefp, exprp}};
nodep->replaceWith(newinitp);
VL_DO_DANGLING(pushDeletep(nodep), nodep);
FileLine* const flp = nodep->fileline();
AstInitial* const newinitp = new AstInitial{flp, new AstAssign{flp, varrefp, exprp}};
procp->replaceWith(newinitp);
VL_DO_DANGLING(pushDeletep(procp), procp);
// Set the initial value right in the variable so we can constant propagate
AstNode* const initvaluep = exprp->cloneTree(false);
varrefp->varp()->valuep(initvaluep);

9
src/V3Coverage.cpp
View File

@ -282,7 +282,14 @@ class CoverageVisitor final : public VNVisitor {
}
iterateChildren(nodep);
}
void visit(AstAlways* nodep) override {
if (nodep->keyword() == VAlwaysKwd::CONT_ASSIGN) {
// Don't want line coverage for it, iterate for expression/toggle coverage only
iterateChildren(nodep);
return;
}
iterateProcedure(nodep);
}
void visit(AstNodeProcedure* nodep) override { iterateProcedure(nodep); }
void visit(AstLoop* nodep) override {
UASSERT_OBJ(!nodep->contsp(), nodep, "'contsp' only used before LinkJump");

51
src/V3DfgAstToDfg.cpp
View File

@ -176,33 +176,35 @@ class AstToDfgVisitor final : public VNVisitor {
}
}
// Convert AstAssignW to DfgLogic, return true if successful.
bool convert(AstAssignW* nodep) {
// Cannot handle assignment with timing control
if (nodep->timingControlp()) return false;
// Potentially convertible block
++m_ctx.m_inputs;
// Gather written variables, give up if any are not supported
const std::unique_ptr<std::vector<DfgVertexVar*>> oVarpsp = gatherWritten(nodep);
if (!oVarpsp) return false;
// Gather read variables, give up if any are not supported
const std::unique_ptr<std::vector<DfgVertexVar*>> iVarpsp = gatherRead(nodep);
if (!iVarpsp) return false;
// Create the DfgLogic
DfgLogic* const logicp = new DfgLogic{m_dfg, nodep, m_scopep};
// Connect it up
connect(*logicp, *iVarpsp, *oVarpsp);
// Done
++m_ctx.m_representable;
return true;
}
// Convert AstAlways to DfgLogic, return true if successful.
bool convert(AstAlways* nodep) {
const VAlwaysKwd kwd = nodep->keyword();
if (kwd == VAlwaysKwd::CONT_ASSIGN) {
// TODO: simplify once CFG analysis can handle arrays
if (AstAssignW* const ap = VN_CAST(nodep->stmtsp(), AssignW)) {
if (ap->nextp()) return false;
// Cannot handle assignment with timing control
if (ap->timingControlp()) return false;
// Potentially convertible block
++m_ctx.m_inputs;
// Gather written variables, give up if any are not supported
const std::unique_ptr<std::vector<DfgVertexVar*>> oVarpsp = gatherWritten(ap);
if (!oVarpsp) return false;
// Gather read variables, give up if any are not supported
const std::unique_ptr<std::vector<DfgVertexVar*>> iVarpsp = gatherRead(ap);
if (!iVarpsp) return false;
// Create the DfgLogic
DfgLogic* const logicp = new DfgLogic{m_dfg, nodep, m_scopep, nullptr};
// Connect it up
connect(*logicp, *iVarpsp, *oVarpsp);
// Done
++m_ctx.m_representable;
return true;
}
}
// Can only handle combinational logic
if (nodep->sentreep()) return false;
const VAlwaysKwd kwd = nodep->keyword();
if (kwd != VAlwaysKwd::ALWAYS && kwd != VAlwaysKwd::ALWAYS_COMB) return false;
// Potentially convertible block
@ -261,9 +263,6 @@ class AstToDfgVisitor final : public VNVisitor {
void visit(AstNodeProcedure* nodep) override { markReferenced(nodep); }
// Potentially representable constructs
void visit(AstAssignW* nodep) override {
if (!convert(nodep)) markReferenced(nodep);
}
void visit(AstAlways* nodep) override {
if (!convert(nodep)) markReferenced(nodep);
}

3
src/V3DfgDfgToAst.cpp
View File

@ -164,7 +164,8 @@ class DfgToAstVisitor final : DfgVisitor {
}
// Otherwise create an AssignW
m_containerp->addStmtsp(new AstAssignW{flp, lhsp, rhsp});
AstAssignW* const ap = new AstAssignW{flp, lhsp, rhsp};
m_containerp->addStmtsp(new AstAlways{ap});
}
void convertDriver(FileLine* flp, AstNodeExpr* lhsp, DfgVertex* driverp) {

5
src/V3DfgOptimizer.cpp
View File

@ -138,8 +138,9 @@ class DataflowExtractVisitor final : public VNVisitor {
cnodep->replaceWith(new AstVarRef{flp, varp, VAccess::READ});
// Add assignment driving temporary variable
modp->addStmtsp(
new AstAssignW{flp, new AstVarRef{flp, varp, VAccess::WRITE}, cnodep});
AstAssignW* const ap
= new AstAssignW{flp, new AstVarRef{flp, varp, VAccess::WRITE}, cnodep};
modp->addStmtsp(new AstAlways{ap});
}
}
}

13
src/V3DfgSynthesize.cpp
View File

@ -1482,7 +1482,7 @@ class AstToDfgSynthesize final {
}
// TODO: computePropagatedDrivers cannot handle arrays, should
// never happen with AssignW
// never happen with simple continous assignments
if (!resp->isPacked()) {
++m_ctx.m_synt.nonSynArray;
return true; // Not OK, give up
@ -1597,8 +1597,9 @@ class AstToDfgSynthesize final {
VL_RESTORER(m_logicp);
m_logicp = &vtx;
if (AstAssignW* const nodep = VN_CAST(vtx.nodep(), AssignW)) {
if (!synthesizeAssignW(nodep)) return false;
if (AstAssignW* const ap = VN_CAST(vtx.nodep()->stmtsp(), AssignW)) {
if (ap->nextp()) return false;
if (!synthesizeAssignW(ap)) return false;
++m_ctx.m_synt.synthAssign;
return true;
}
@ -1908,12 +1909,12 @@ static void dfgSelectLogicForSynthesis(DfgGraph& dfg) {
});
}
// Synthesize all AssignW and simple blocks driving exactly one variable
// This is approximately the old default behaviour of Dfg
// Synthesize all continuous assignments and simple blocks driving exactly
// one variable. This is approximately the old default behaviour of Dfg.
for (DfgVertex& vtx : dfg.opVertices()) {
DfgLogic* const logicp = vtx.cast<DfgLogic>();
if (!logicp) continue;
if (VN_IS(logicp->nodep(), AssignW)) {
if (logicp->nodep()->keyword() == VAlwaysKwd::CONT_ASSIGN) {
worklist.push_front(*logicp);
continue;
}

10
src/V3DfgVertices.h
View File

@ -457,7 +457,7 @@ public:
class DfgLogic final : public DfgVertexVariadic {
// Generic vertex representing a whole combinational process
AstNode* const m_nodep; // The Ast logic represented by this vertex
AstAlways* const m_nodep; // The Ast logic represented by this vertex
AstScope* const m_scopep; // The AstScope m_nodep is under, iff scoped
const std::unique_ptr<CfgGraph> m_cfgp;
std::vector<DfgVertex*> m_synth; // Vertices this logic was synthesized into
@ -466,12 +466,6 @@ class DfgLogic final : public DfgVertexVariadic {
bool m_reverted = false; // Logic was synthesized (in part if non synthesizable) then reverted
public:
DfgLogic(DfgGraph& dfg, AstAssignW* nodep, AstScope* scopep)
: DfgVertexVariadic{dfg, dfgType(), nodep->fileline(), DfgDataType::null()}
, m_nodep{nodep}
, m_scopep{scopep}
, m_cfgp{nullptr} {}
DfgLogic(DfgGraph& dfg, AstAlways* nodep, AstScope* scopep, std::unique_ptr<CfgGraph> cfgp)
: DfgVertexVariadic{dfg, dfgType(), nodep->fileline(), DfgDataType::null()}
, m_nodep{nodep}
@ -486,7 +480,7 @@ public:
void addInput(DfgVertexVar* varp) { newInput()->relinkSrcp(varp); }
// Accessors
AstNode* nodep() const { return m_nodep; }
AstAlways* nodep() const { return m_nodep; }
AstScope* scopep() const { return m_scopep; }
CfgGraph& cfg() { return *m_cfgp; }
const CfgGraph& cfg() const { return *m_cfgp; }

16
src/V3EmitV.cpp
View File

@ -170,6 +170,20 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst {
void visit(AstInitialAutomatic* nodep) override { iterateChildrenConst(nodep); }
void visit(AstInitialStatic* nodep) override { iterateChildrenConst(nodep); }
void visit(AstAlways* nodep) override {
if (const AstAssignW* const ap = VN_CAST(nodep->stmtsp(), AssignW)) {
if (!ap->nextp()) {
putfs(nodep, "assign ");
if (AstNode* const tcp = ap->timingControlp()) {
iterateAndNextConstNull(tcp);
putbs(" ");
}
iterateAndNextConstNull(ap->lhsp());
putbs(" = ");
iterateAndNextConstNull(ap->rhsp());
if (!m_suppressSemi) puts(";\n");
return;
}
}
putfs(nodep, "always ");
if (m_sentreep) {
iterateAndNextConstNull(m_sentreep);
@ -214,7 +228,7 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst {
if (!m_suppressSemi) puts(";\n");
}
void visit(AstAssignW* nodep) override {
putfs(nodep, "assign ");
putfs(nodep, "continuous assign ");
iterateAndNextConstNull(nodep->lhsp());
putbs(" = ");
iterateAndNextConstNull(nodep->rhsp());

9
src/V3Force.cpp
View File

@ -363,6 +363,15 @@ class ForceReplaceVisitor final : public VNVisitor {
void visit(AstCFunc* nodep) override { iterateLogic(nodep); }
void visit(AstCoverToggle* nodep) override { iterateLogic(nodep); }
void visit(AstNodeProcedure* nodep) override { iterateLogic(nodep); }
void visit(AstAlways* nodep) override {
// TODO: this is the old behavioud prior to moving AssignW under Always.
// Review if this is appropriate or if we are missing something...
if (nodep->keyword() == VAlwaysKwd::CONT_ASSIGN) {
iterateChildren(nodep);
return;
}
iterateLogic(nodep);
}
void visit(AstSenItem* nodep) override { iterateLogic(nodep); }
void visit(AstVarRef* nodep) override {
if (ForceState::isNotReplaceable(nodep)) return;

11
src/V3Gate.cpp
View File

@ -257,9 +257,6 @@ class GateBuildVisitor final : public VNVisitorConst {
const bool slow = VN_IS(nodep, Initial) || VN_IS(nodep, Final);
iterateLogic(nodep, slow, nodep->isJustOneBodyStmt() ? nullptr : "Multiple Stmts");
}
void visit(AstAssignW* nodep) override { //
iterateLogic(nodep);
}
void visit(AstCoverToggle* nodep) override {
iterateLogic(nodep, false, "CoverToggle", "CoverToggle");
}
@ -1121,13 +1118,15 @@ class GateMergeAssignments final {
void process(GateVarVertex* vVtxp) {
GateLogicVertex* prevLVtxp = nullptr;
AstNodeAssign* prevAssignp = nullptr;
AstAssignW* prevAssignp = nullptr;
for (V3GraphEdge* const edgep : vVtxp->inEdges().unlinkable()) {
GateLogicVertex* const lVtxp = edgep->fromp()->as<GateLogicVertex>();
if (!lVtxp->outSize1()) continue;
AstNodeAssign* const assignp = VN_CAST(lVtxp->nodep(), NodeAssign);
AstAlways* const alwaysp = VN_CAST(lVtxp->nodep(), Always);
if (!alwaysp || !alwaysp->stmtsp() || alwaysp->stmtsp()->nextp()) return;
AstAssignW* const assignp = VN_CAST(alwaysp->stmtsp(), AssignW);
if (!assignp) continue;
if (!VN_IS(assignp->lhsp(), Sel)) continue;
@ -1139,8 +1138,6 @@ class GateMergeAssignments final {
continue;
}
UASSERT_OBJ(prevAssignp->type() == assignp->type(), assignp, "Mismatched types");
AstSel* const prevSelp = VN_AS(prevAssignp->lhsp(), Sel);
AstSel* const currSelp = VN_AS(assignp->lhsp(), Sel);

12
src/V3Inline.cpp
View File

@ -171,7 +171,7 @@ class InlineMarkVisitor final : public VNVisitor {
iterateChildren(nodep);
}
void visit(AstAlways* nodep) override {
m_modp->user4Inc(); // statement count
if (nodep->keyword() != VAlwaysKwd::CONT_ASSIGN) nodep->user4Inc(); // statement count
iterateChildren(nodep);
}
void visit(AstNodeAssign* nodep) override {
@ -480,7 +480,9 @@ void connectPort(AstNodeModule* modp, AstVar* nodep, AstNodeExpr* pinExprp) {
// the port variable. The constant can still be inlined, in which case
// this is needed for tracing the inlined port variable.
if (AstConst* const pinp = VN_CAST(pinExprp, Const)) {
modp->addStmtsp(new AstAssignW{flp, portRef(VAccess::WRITE), pinp->cloneTree(false)});
AstAssignW* const ap
= new AstAssignW{flp, portRef(VAccess::WRITE), pinp->cloneTree(false)};
modp->addStmtsp(new AstAlways{ap});
return;
}
@ -516,9 +518,11 @@ void connectPort(AstNodeModule* modp, AstVar* nodep, AstNodeExpr* pinExprp) {
// Otherwise create the continuous assignment between the port var and the pin expression
UINFO(6, "Not inlning port variable: " << nodep);
if (nodep->direction() == VDirection::INPUT) {
modp->addStmtsp(new AstAssignW{flp, portRef(VAccess::WRITE), pinRef(VAccess::READ)});
AstAssignW* const ap = new AstAssignW{flp, portRef(VAccess::WRITE), pinRef(VAccess::READ)};
modp->addStmtsp(new AstAlways{ap});
} else if (nodep->direction() == VDirection::OUTPUT) {
modp->addStmtsp(new AstAssignW{flp, pinRef(VAccess::WRITE), portRef(VAccess::READ)});
AstAssignW* const ap = new AstAssignW{flp, pinRef(VAccess::WRITE), portRef(VAccess::READ)};
modp->addStmtsp(new AstAlways{ap});
} else {
pinExprp->v3fatalSrc("V3Tristate left INOUT port");
}

8
src/V3Inst.cpp
View File

@ -73,16 +73,16 @@ class InstVisitor final : public VNVisitor {
AstNodeExpr* const rhsp = new AstVarXRef{exprp->fileline(), nodep->modVarp(),
m_cellp->name(), VAccess::READ};
AstAssignW* const assp = new AstAssignW{exprp->fileline(), exprp, rhsp};
m_cellp->addNextHere(assp);
m_cellp->addNextHere(new AstAlways{assp});
} else if (nodep->modVarp()->isNonOutput()) {
// Don't bother moving constants now,
// we'll be pushing the const down to the cell soon enough.
AstNode* const assp
AstAssignW* const assp
= new AstAssignW{exprp->fileline(),
new AstVarXRef{exprp->fileline(), nodep->modVarp(),
m_cellp->name(), VAccess::WRITE},
exprp};
m_cellp->addNextHere(assp);
m_cellp->addNextHere(new AstAlways{assp});
UINFOTREE(9, assp, "", "_new");
} else if (nodep->modVarp()->isIfaceRef()
|| (VN_IS(nodep->modVarp()->dtypep()->skipRefp(), UnpackArrayDType)
@ -676,7 +676,7 @@ public:
pinexprp};
pinp->exprp(new AstVarRef{pinexprp->fileline(), newvarp, VAccess::READ});
}
if (assignp) cellp->addNextHere(assignp);
if (assignp) cellp->addNextHere(new AstAlways{assignp});
// UINFOTREE(1, pinp, "", "out");
// UINFOTREE(1, assignp, "", "aout");
}

2
src/V3LinkDot.cpp
View File

@ -4220,7 +4220,7 @@ class LinkDotResolveVisitor final : public VNVisitor {
nodep->fileline(), new AstVarRef{nodep->fileline(), nodep, VAccess::WRITE},
new AstVarRef{nodep->fileline(), aliasp, VAccess::READ}};
assignp->user2(true);
nodep->addNextHere(assignp);
nodep->addNextHere(new AstAlways{assignp});
// Propagate attributes of the replaced variable,
// because all references to it are replaced with references to the alias variable
aliasp->varp()->propagateAttrFrom(nodep->varp());

9
src/V3LinkResolve.cpp
View File

@ -454,10 +454,11 @@ class LinkResolveVisitor final : public VNVisitor {
}
varoutp = varp;
// Tie off
m_modp->addStmtsp(
new AstAssignW{varp->fileline(),
new AstVarRef{varp->fileline(), varp, VAccess::WRITE},
new AstConst{varp->fileline(), AstConst::BitFalse{}}});
AstAssignW* const ap
= new AstAssignW{varp->fileline(),
new AstVarRef{varp->fileline(), varp, VAccess::WRITE},
new AstConst{varp->fileline(), AstConst::BitFalse{}}};
m_modp->addStmtsp(new AstAlways{ap});
} else {
varp->v3error("Only inputs and outputs are allowed in udp modules");
}

3
src/V3OrderGraphBuilder.cpp
View File

@ -327,9 +327,6 @@ class OrderGraphBuilder final : public VNVisitor {
nodep->v3fatalSrc("AstFinal should not need ordering");
} // LCOV_EXCL_STOP
//--- SystemVerilog continuous assignments
void visit(AstAssignW* nodep) override { iterateLogic(nodep); }
//--- Verilator concoctions
void visit(AstCoverToggle* nodep) override { //
iterateLogic(nodep);

10
src/V3ParseGrammar.cpp
View File

@ -96,7 +96,7 @@ AstArg* V3ParseGrammar::argWrapList(AstNodeExpr* nodep) {
return outp;
}
AstNode* V3ParseGrammar::createSupplyExpr(FileLine* fileline, const string& name, int value) {
AstAssignW* V3ParseGrammar::createSupplyExpr(FileLine* fileline, const string& name, int value) {
AstAssignW* assignp = new AstAssignW{fileline, new AstParseRef{fileline, name},
value ? new AstConst{fileline, AstConst::All1{}}
: new AstConst{fileline, AstConst::All0{}}};
@ -253,12 +253,12 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
}
if (GRAMMARP->m_varDecl == VVarType::SUPPLY0) {
AstNode::addNext<AstNode, AstNode>(
nodep, V3ParseGrammar::createSupplyExpr(fileline, nodep->name(), 0));
AstAssignW* const ap = V3ParseGrammar::createSupplyExpr(fileline, nodep->name(), 0);
AstNode::addNext<AstNode, AstNode>(nodep, new AstAlways{ap});
}
if (GRAMMARP->m_varDecl == VVarType::SUPPLY1) {
AstNode::addNext<AstNode, AstNode>(
nodep, V3ParseGrammar::createSupplyExpr(fileline, nodep->name(), 1));
AstAssignW* const ap = V3ParseGrammar::createSupplyExpr(fileline, nodep->name(), 1);
AstNode::addNext<AstNode, AstNode>(nodep, new AstAlways{ap});
}
if (VN_IS(dtypep, ParseTypeDType)) {
// Parser needs to know what is a type

2
src/V3ParseGrammar.h
View File

@ -73,7 +73,7 @@ public:
bool isPacked) VL_MT_DISABLED;
AstVar* createVariable(FileLine* fileline, const string& name, AstNodeRange* arrayp,
AstNode* attrsp) VL_MT_DISABLED;
AstNode* createSupplyExpr(FileLine* fileline, const string& name, int value) VL_MT_DISABLED;
AstAssignW* createSupplyExpr(FileLine* fileline, const string& name, int value) VL_MT_DISABLED;
AstText* createTextQuoted(FileLine* fileline, const string& text) {
string newtext = singletonp()->unquoteString(fileline, text);
return new AstText{fileline, newtext};

9
src/V3SchedAcyclic.cpp
View File

@ -103,8 +103,13 @@ class Graph final : public V3Graph {
string loopsVertexCb(V3GraphVertex* vtxp) override {
if (SchedAcyclicLogicVertex* const lvtxp = vtxp->cast<SchedAcyclicLogicVertex>()) {
AstNode* const logicp = lvtxp->logicp();
return logicp->fileline()->warnOther()
+ " Example path: " + logicp->prettyTypeName() + "\n";
std::string logicName = logicp->prettyTypeName();
if (const AstAlways* const alwaysp = VN_CAST(logicp, Always)) {
if (alwaysp->keyword() == VAlwaysKwd::CONT_ASSIGN) {
logicName = "ASSIGNW"; // Keep using historiacl name until we have better
}
}
return logicp->fileline()->warnOther() + " Example path: " + logicName + "\n";
} else {
SchedAcyclicVarVertex* const vvtxp = vtxp->as<SchedAcyclicVarVertex>();
AstVarScope* const vscp = vvtxp->vscp();

10
src/V3SchedVirtIface.cpp
View File

@ -19,9 +19,6 @@
// Each interface type written to via virtual interface, or written to normally but read via
// virtual interface:
// Create a trigger var for it
// Each AssignW:
// If it writes to a virtual interface, or to a variable read via virtual interface:
// Convert to an always
// Each statement:
// If it writes to a virtual interface, or to a variable read via virtual interface:
// Set the corresponding trigger to 1
@ -166,13 +163,6 @@ private:
m_trigAssignMemberVarp = nullptr;
iterateChildren(nodep);
}
void visit(AstAssignW* nodep) override {
if (writesToVirtIface(nodep)) {
// Convert to always, as we have to assign the trigger var
nodep->convertToAlways();
VL_DO_DANGLING(pushDeletep(nodep), nodep);
}
}
void visit(AstNodeIf* nodep) override {
unsupportedWriteToVirtIface(nodep->condp(), "if condition");
{

9
src/V3Scope.cpp
View File

@ -224,14 +224,6 @@ class ScopeVisitor final : public VNVisitor {
m_scopep->addBlocksp(clonep);
iterateChildren(clonep); // We iterate under the *clone*
}
void visit(AstAssignW* nodep) override {
// Add to list of blocks under this scope
UINFO(4, " Move " << nodep);
AstNode* const clonep = nodep->cloneTree(false);
nodep->user2p(clonep);
m_scopep->addBlocksp(clonep);
iterateChildren(clonep); // We iterate under the *clone*
}
void visit(AstCoverToggle* nodep) override {
// Add to list of blocks under this scope
UINFO(4, " Move " << nodep);
@ -355,7 +347,6 @@ class ScopeCleanupVisitor final : public VNVisitor {
void visit(AstNodeProcedure* nodep) override { movedDeleteOrIterate(nodep); }
void visit(AstAlias* nodep) override { movedDeleteOrIterate(nodep); }
void visit(AstAliasScope* nodep) override { movedDeleteOrIterate(nodep); }
void visit(AstAssignW* nodep) override { movedDeleteOrIterate(nodep); }
void visit(AstCoverToggle* nodep) override { movedDeleteOrIterate(nodep); }
void visit(AstNodeFTask* nodep) override { movedDeleteOrIterate(nodep); }
void visit(AstCFunc* nodep) override { movedDeleteOrIterate(nodep); }

60
src/V3SplitVar.cpp
View File

@ -128,15 +128,6 @@ struct SplitVarImpl VL_NOT_FINAL {
// AstNodeModule::user1() -> Block number counter for generating unique names
const VNUser1InUse m_user1InUse; // Only used in SplitUnpackedVarVisitor
static AstNodeAssign* newAssign(FileLine* fileline, AstNodeExpr* lhsp, AstNodeExpr* rhsp,
const AstVar* varp) {
if (varp->isFuncLocal() || varp->isFuncReturn()) {
return new AstAssign{fileline, lhsp, rhsp};
} else {
return new AstAssignW{fileline, lhsp, rhsp};
}
}
// These check functions return valid pointer to the reason text if a variable cannot be split.
// Check if a var type can be split
@ -622,25 +613,25 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
AstNode* const refp = lhsp;
UINFO(9, "Creating assign idx:" << i << " + " << start_idx);
if (!lvalue) std::swap(lhsp, rhsp);
AstNode* newassignp;
if (use_simple_assign) {
AstNode* const insertp = context;
newassignp = new AstAssign{fl, lhsp, rhsp};
AstAssign* const ap = new AstAssign{fl, lhsp, rhsp};
if (lvalue) {
// If varp is LHS, this assignment must appear after the original
// assignment(context).
insertp->addNextHere(newassignp);
context->addNextHere(ap);
} else {
// If varp is RHS, this assignment comes just before the original assignment
insertp->addHereThisAsNext(newassignp);
context->addHereThisAsNext(ap);
}
UASSERT_OBJ(!m_contextp, m_contextp, "must be null");
setContextAndIterate(ap, refp);
} else {
newassignp = new AstAssignW{fl, lhsp, rhsp};
AstAssignW* const ap = new AstAssignW{fl, lhsp, rhsp};
// Continuous assignment must be in module context.
varp->addNextHere(newassignp);
varp->addNextHere(new AstAlways{ap});
UASSERT_OBJ(!m_contextp, m_contextp, "must be null");
setContextAndIterate(ap, refp);
}
UASSERT_OBJ(!m_contextp, m_contextp, "must be null");
setContextAndIterate(newassignp, refp);
}
return newVarRef(fl, varp, lvalue ? VAccess::WRITE : VAccess::READ);
}
@ -655,18 +646,19 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
newVarRef(fl, vars.at(i), !lvalue ? VAccess::WRITE : VAccess::READ)};
AstNodeExpr* const lhsp = nodes[lvalue ? 0 : 1];
AstNodeExpr* const rhsp = nodes[lvalue ? 1 : 0];
AstNodeAssign* const assignp = newAssign(fl, lhsp, rhsp, varp);
if (insertp) {
AstAssign* const ap = new AstAssign{fl, lhsp, rhsp};
if (lvalue) { // Just after writing to the temporary variable
insertp->addNextHere(assignp);
insertp->addNextHere(ap);
} else { // Just before reading the temporary variable
insertp->addHereThisAsNext(assignp);
insertp->addHereThisAsNext(ap);
}
setContextAndIterate(ap, nodes[1]);
} else {
UASSERT_OBJ(VN_IS(assignp, AssignW), varp, "must be AssginW");
vars.at(i)->addNextHere(assignp);
AstAssignW* const ap = new AstAssignW{fl, lhsp, rhsp};
vars.at(i)->addNextHere(new AstAlways{ap});
setContextAndIterate(ap, nodes[1]);
}
setContextAndIterate(assignp, nodes[1]);
}
}
// cppcheck-has-bug-suppress constParameter
@ -1051,15 +1043,16 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
var.lsb() - portLsb, var.bitwidth()};
AstNodeExpr* lhsp = new AstVarRef{fl, var.varp(), in ? VAccess::WRITE : VAccess::READ};
if (!in) std::swap(lhsp, rhsp);
AstNodeAssign* const assignp = newAssign(fl, lhsp, rhsp, portp);
if (insertp) {
AstAssign* const ap = new AstAssign{fl, lhsp, rhsp};
if (in) {
insertp->addHereThisAsNext(assignp);
insertp->addHereThisAsNext(ap);
} else {
insertp->addNextHere(assignp);
insertp->addNextHere(ap);
}
} else {
var.varp()->addNextHere(assignp);
AstAssignW* const ap = new AstAssignW{fl, lhsp, rhsp};
var.varp()->addNextHere(new AstAlways{ap});
}
}
}
@ -1184,8 +1177,15 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
rhsp = new AstConcat{fl, new AstVarRef{fl, vars[i].varp(), VAccess::READ},
rhsp};
}
varp->addNextHere(
newAssign(fl, new AstVarRef{fl, varp, VAccess::WRITE}, rhsp, varp));
if (varp->isFuncLocal() || varp->isFuncReturn()) {
AstAssign* const ap
= new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE}, rhsp};
varp->addNextHere(ap);
} else {
AstAssignW* const ap
= new AstAssignW{fl, new AstVarRef{fl, varp, VAccess::WRITE}, rhsp};
varp->addNextHere(new AstAlways{ap});
}
} else { // the original variable is not used anymore.
VL_DO_DANGLING(varp->unlinkFrBack()->deleteTree(), varp);
}

19
src/V3Task.cpp
View File

@ -107,7 +107,6 @@ class TaskStateVisitor final : public VNVisitor {
// MEMBERS
VarToScopeMap m_varToScopeMap; // Map for Var -> VarScope mappings
FuncToClassMap m_funcToClassMap; // Map for ctor func -> class
AstAssignW* m_assignwp = nullptr; // Current assignment
AstNodeFTask* m_ctorp = nullptr; // Class constructor
AstClass* m_classp = nullptr; // Current class
V3Graph m_callGraph; // Task call graph
@ -144,13 +143,6 @@ public:
void checkPurity(AstNodeFTask* nodep) { checkPurity(nodep, getFTaskVertex(nodep)); }
private:
void convertAssignWToAlways() {
// Wire assigns must become always statements to deal with insertion
// of multiple statements. Perhaps someday make all wassigns into always's?
UINFO(5, " IM_WireRep " << m_assignwp);
m_assignwp->convertToAlways();
VL_DO_CLEAR(pushDeletep(m_assignwp), m_assignwp = nullptr);
}
void checkPurity(AstNodeFTask* nodep, TaskBaseVertex* vxp) {
if (nodep->recursive()) return; // Impure, but no warning
if (!vxp->pure()) {
@ -193,18 +185,7 @@ private:
}
iterateChildren(nodep);
}
void visit(AstAssignW* nodep) override {
VL_RESTORER(m_assignwp);
m_assignwp = nodep;
VL_DO_DANGLING(iterateChildren(nodep), nodep); // May delete nodep.
}
void visit(AstExprStmt* nodep) override {
if (m_assignwp) convertAssignWToAlways();
iterateChildren(nodep);
}
void visit(AstNodeFTaskRef* nodep) override {
// Includes handling AstMethodCall, AstNew
if (m_assignwp) convertAssignWToAlways();
// We make multiple edges if a task is called multiple times from another task.
UASSERT_OBJ(nodep->taskp(), nodep, "Unlinked task");
TaskFTaskVertex* const taskVtxp = getFTaskVertex(nodep->taskp());

30
src/V3Timing.cpp
View File

@ -381,6 +381,10 @@ class TimingSuspendableVisitor final : public VNVisitor {
if (!VN_IS(m_procp, NodeProcedure)) v3Global.setUsesTiming();
visit(static_cast<AstNode*>(nodep));
}
void visit(AstAssignW* nodep) override {
if (nodep->timingControlp()) v3Global.setUsesTiming();
// Containing process will not suspend, don't mark it
}
void visit(AstNode* nodep) override {
if (nodep->isTimingControl()) {
v3Global.setUsesTiming();
@ -1096,24 +1100,30 @@ class TimingControlVisitor final : public VNVisitor {
refp->varp()->fileline()->modifyWarnOff(V3ErrorCode::UNOPTFLAT, true);
}
});
// Convert it to an always; the new assign with intra delay will be handled by
// Should be under an always
AstAlways* const alwaysp = VN_AS(m_procp, Always);
// Convert it to an Assign; the new assign with intra delay will be handled by
// visit(AstNodeAssign*)
AstAlways* const alwaysp = nodep->convertToAlways();
visit(alwaysp); // Visit now as we need to do some post-processing
VL_DO_DANGLING(nodep->deleteTree(), nodep);
AstNodeExpr* const lhs1p = nodep->lhsp()->unlinkFrBack();
AstNodeExpr* const rhs1p = nodep->rhsp()->unlinkFrBack();
AstNode* const controlp = nodep->timingControlp()->unlinkFrBack();
AstAssign* const assignp = new AstAssign{nodep->fileline(), lhs1p, rhs1p, controlp};
// Put the assignment in a fork..join_none.
AstBegin* const beginp = new AstBegin{flp, "", assignp, false};
AstFork* const forkp = new AstFork{flp, "", beginp};
forkp->joinType(VJoinType::JOIN_NONE);
nodep->replaceWith(forkp);
VL_DO_DANGLING(pushDeletep(nodep), nodep);
visit(forkp); // Visit now as we need to do some post-processing
// IEEE 1800-2023 10.3.3 - if the RHS value differs from the currently scheduled value to
// be assigned, the currently scheduled assignment is descheduled. To keep track if an
// assignment should be descheduled, each scheduled assignment event has a 'generation',
// and if at assignment time its generation differs from the current generation, it won't
// be performed
AstFork* const forkp = VN_AS(alwaysp->stmtsp(), Fork);
UASSERT_OBJ(forkp, alwaysp, "Fork should be there from convertToAlways()");
AstBegin* const beginp = VN_AS(forkp->stmtsp(), Begin);
UASSERT_OBJ(beginp, alwaysp, "Begin should be there from convertToAlways()");
AstAssign* const preAssignp = VN_AS(beginp->stmtsp(), Assign);
UASSERT_OBJ(preAssignp, alwaysp, "Pre-assign should be there from convertToAlways()");
UASSERT_OBJ(preAssignp, alwaysp, "Pre-assign should be there from visit(AstFork)");
AstAssign* const postAssignp = VN_AS(preAssignp->nextp()->nextp(), Assign);
UASSERT_OBJ(postAssignp, alwaysp, "Post-assign should be there from convertToAlways()");
UASSERT_OBJ(postAssignp, alwaysp, "Post-assign should be there from visit(AstFork)");
// Increment generation and copy it to a local
AstVarScope* const generationVarp
= createTemp(flp, m_contAsgnGenNames.get(alwaysp), alwaysp->findUInt64DType());

71
src/V3Tristate.cpp
View File

@ -625,10 +625,10 @@ class TristateVisitor final : public TristateBaseVisitor {
AstConst* const constp = newAllZerosOrOnes(varp, false);
AstVarRef* const varrefp
= new AstVarRef{varp->fileline(), varp, VAccess::WRITE};
AstNode* const newp = new AstAssignW{varp->fileline(), varrefp, constp};
AstAssignW* const newp = new AstAssignW{varp->fileline(), varrefp, constp};
UINFO(9, " newoev " << newp);
varrefp->user1p(newAllZerosOrOnes(varp, false));
nodep->addStmtsp(newp);
nodep->addStmtsp(new AstAlways{newp});
mapInsertLhsVarRef(varrefp); // insertTristates will convert
// // to a varref to the __out# variable
}
@ -682,11 +682,11 @@ class TristateVisitor final : public TristateBaseVisitor {
UINFO(9, " newenlhsp " << newEnLhsp);
nodep->addStmtsp(newEnLhsp);
AstNode* const enLhspAssignp = new AstAssignW{
AstAssignW* const enLhspAssignp = new AstAssignW{
refp->fileline(), new AstVarRef{refp->fileline(), newEnLhsp, VAccess::WRITE},
getEnp(refp)};
UINFO(9, " newenlhspAssignp " << enLhspAssignp);
nodep->addStmtsp(enLhspAssignp);
nodep->addStmtsp(new AstAlways{enLhspAssignp});
// now append this driver to the driver logic.
AstNodeExpr* const ref1p = new AstVarRef{refp->fileline(), newLhsp, VAccess::READ};
@ -699,15 +699,15 @@ class TristateVisitor final : public TristateBaseVisitor {
AstNodeExpr* const ref3p = new AstVarRef{refp->fileline(), newEnLhsp, VAccess::READ};
enp = (!enp) ? ref3p : new AstOr{ref3p->fileline(), enp, ref3p};
}
AstNode* const assp = new AstAssignW{
AstAssignW* const assp = new AstAssignW{
varp->fileline(), new AstVarRef{varp->fileline(), varp, VAccess::WRITE}, orp};
UINFO(9, " newassp " << assp);
nodep->addStmtsp(assp);
nodep->addStmtsp(new AstAlways{assp});
AstNode* const enAssp = new AstAssignW{
AstAssignW* const enAssp = new AstAssignW{
envarp->fileline(), new AstVarRef{envarp->fileline(), envarp, VAccess::WRITE}, enp};
UINFO(9, " newenassp " << enAssp);
nodep->addStmtsp(enAssp);
nodep->addStmtsp(new AstAlways{enAssp});
}
void insertTristatesSignal(AstNodeModule* nodep, AstVar* const invarp, RefStrengthVec* refsp) {
@ -825,15 +825,15 @@ class TristateVisitor final : public TristateBaseVisitor {
AstAssignW* const enAssp = new AstAssignW{
enp->fileline(), new AstVarRef{envarp->fileline(), envarp, VAccess::WRITE}, enp};
UINFOTREE(9, enAssp, "", "enAssp");
nodep->addStmtsp(enAssp);
nodep->addStmtsp(new AstAlways{enAssp});
}
// __out (child) or <in> (parent) = drive-value expression
AstNode* const assp = new AstAssignW{
AstAssignW* const assp = new AstAssignW{
lhsp->fileline(), new AstVarRef{lhsp->fileline(), lhsp, VAccess::WRITE}, orp};
assp->user2(U2_BOTH); // Don't process further; already resolved
UINFOTREE(9, assp, "", "lhsp-eqn");
nodep->addStmtsp(assp);
nodep->addStmtsp(new AstAlways{assp});
// If this is a top-level inout, make sure that the INOUT pins get __en and __out
if (v3Global.opt.pinsInoutEnables() && isTopInout) {
@ -848,8 +848,8 @@ class TristateVisitor final : public TristateBaseVisitor {
}
}
bool isOnlyAssignmentIsToLhsVar(AstAssignW* const nodep) {
if (AstVarRef* const varRefp = VN_CAST(nodep->lhsp(), VarRef)) {
bool isOnlyAssignmentIsToLhsVar(const AstAssignW* const nodep) {
if (const AstVarRef* const varRefp = VN_CAST(nodep->lhsp(), VarRef)) {
auto foundIt = m_assigns.find(varRefp->varp());
if (foundIt != m_assigns.end()) {
auto const& assignsToVar = foundIt->second;
@ -873,15 +873,15 @@ class TristateVisitor final : public TristateBaseVisitor {
}
}
uint8_t getStrength(AstAssignW* const nodep, bool value) {
uint8_t getStrength(const AstAssignW* const nodep, bool value) {
if (AstStrengthSpec* const strengthSpec = nodep->strengthSpecp()) {
return value ? strengthSpec->strength1() : strengthSpec->strength0();
}
return VStrength::STRONG; // default strength is strong
}
bool assignmentOfValueOnAllBits(AstAssignW* const nodep, bool value) {
if (AstConst* const constp = VN_CAST(nodep->rhsp(), Const)) {
bool assignmentOfValueOnAllBits(const AstAssignW* const nodep, bool value) {
if (const AstConst* const constp = VN_CAST(nodep->rhsp(), Const)) {
const V3Number num = constp->num();
return value ? num.isEqAllOnes() : num.isEqZero();
}
@ -890,7 +890,7 @@ class TristateVisitor final : public TristateBaseVisitor {
AstAssignW* getStrongestAssignmentOfValue(const Assigns& assigns, bool value) {
auto maxIt = std::max_element(
assigns.begin(), assigns.end(), [&](AstAssignW* ap, AstAssignW* bp) {
assigns.begin(), assigns.end(), [&](const AstAssignW* ap, const AstAssignW* bp) {
bool valuesOnRhsA = assignmentOfValueOnAllBits(ap, value);
bool valuesOnRhsB = assignmentOfValueOnAllBits(bp, value);
if (!valuesOnRhsA) return valuesOnRhsB;
@ -903,7 +903,7 @@ class TristateVisitor final : public TristateBaseVisitor {
return assignmentOfValueOnAllBits(*maxIt, value) ? *maxIt : nullptr;
}
bool isAssignmentNotStrongerThanStrength(AstAssignW* assignp, uint8_t strength) {
bool isAssignmentNotStrongerThanStrength(const AstAssignW* assignp, uint8_t strength) {
// If the value of the RHS is known and has all bits equal, only strength corresponding to
// its value is taken into account. In opposite case, both strengths are compared.
const uint8_t strength0 = getStrength(assignp, 0);
@ -958,7 +958,7 @@ class TristateVisitor final : public TristateBaseVisitor {
}
}
void removeNotStrongerAssignments(Assigns& assigns, AstAssignW* strongestp,
void removeNotStrongerAssignments(Assigns& assigns, const AstAssignW* strongestp,
uint8_t greatestKnownStrength) {
// Weaker assignments are these assignments that can't change the final value of the net.
// They can be safely removed. Assignments of the same strength are also removed, because
@ -985,12 +985,12 @@ class TristateVisitor final : public TristateBaseVisitor {
for (auto& varpAssigns : m_assigns) {
Assigns& assigns = varpAssigns.second;
if (assigns.size() > 1) {
AstAssignW* const strongest0p = getStrongestAssignmentOfValue(assigns, 0);
AstAssignW* const strongest1p = getStrongestAssignmentOfValue(assigns, 1);
AstAssignW* strongestp = nullptr;
const AstAssignW* const strongest0p = getStrongestAssignmentOfValue(assigns, 0);
const AstAssignW* const strongest1p = getStrongestAssignmentOfValue(assigns, 1);
const AstAssignW* strongestp = nullptr;
uint8_t greatestKnownStrength = 0;
const auto getIfStrongest
= [&](AstAssignW* const strongestCandidatep, bool value) {
= [&](const AstAssignW* const strongestCandidatep, bool value) {
if (!strongestCandidatep) return;
uint8_t strength = getStrength(strongestCandidatep, value);
if (strength >= greatestKnownStrength) {
@ -1017,19 +1017,22 @@ class TristateVisitor final : public TristateBaseVisitor {
for (auto& varpAssigns : m_assigns) {
Assigns& assigns = varpAssigns.second;
if (assigns.size() > 1) {
auto maxIt = std::max_element(
assigns.begin(), assigns.end(), [&](AstAssignW* ap, AstAssignW* bp) {
if (m_tgraph.isTristate(ap)) return !m_tgraph.isTristate(bp);
if (m_tgraph.isTristate(bp)) return false;
const uint8_t minStrengthA
= std::min(getStrength(ap, 0), getStrength(ap, 1));
const uint8_t minStrengthB
= std::min(getStrength(bp, 0), getStrength(bp, 1));
return minStrengthA < minStrengthB;
});
auto maxIt
= std::max_element(assigns.begin(), assigns.end(),
[&](const AstAssignW* ap, const AstAssignW* bp) {
if (m_tgraph.isTristate(ap))
return !m_tgraph.isTristate(bp);
if (m_tgraph.isTristate(bp)) return false;
const uint8_t minStrengthA
= std::min(getStrength(ap, 0), getStrength(ap, 1));
const uint8_t minStrengthB
= std::min(getStrength(bp, 0), getStrength(bp, 1));
return minStrengthA < minStrengthB;
});
// If RHSs of all assignments are tristate, 1st element is returned, so it is
// needed to check if it is non-tristate.
AstAssignW* const strongestp = m_tgraph.isTristate(*maxIt) ? nullptr : *maxIt;
const AstAssignW* const strongestp
= m_tgraph.isTristate(*maxIt) ? nullptr : *maxIt;
if (strongestp) {
uint8_t greatestKnownStrength
= std::min(getStrength(strongestp, 0), getStrength(strongestp, 1));

10
src/V3Unknown.cpp
View File

@ -58,7 +58,6 @@ class UnknownVisitor final : public VNVisitor {
// STATE - for current visit position (use VL_RESTORER)
AstNodeModule* m_modp = nullptr; // Current module
AstNodeFTask* m_ftaskp = nullptr; // Current function/task
AstAssignW* m_assignwp = nullptr; // Current assignment
AstAssignDly* m_assigndlyp = nullptr; // Current assignment
AstNode* m_timingControlp = nullptr; // Current assignment's intra timing control
bool m_constXCvt = false; // Convert X's
@ -82,13 +81,6 @@ class UnknownVisitor final : public VNVisitor {
// but makes a mess in the emitter as lvalue switching is needed. So 4.
// SEL(...) -> temp
// if (COND(LTE(bit<=maxlsb))) ASSIGN(SEL(...)),temp)
if (m_assignwp) {
// Wire assigns must become always statements to deal with insertion
// of multiple statements. Perhaps someday make all wassigns into always's?
UINFO(5, " IM_WireRep " << m_assignwp);
m_assignwp->convertToAlways();
VL_DO_CLEAR(pushDeletep(m_assignwp), m_assignwp = nullptr);
}
const bool needDly = (m_assigndlyp != nullptr);
if (m_assigndlyp) {
// Delayed assignments become normal assignments,
@ -212,9 +204,7 @@ class UnknownVisitor final : public VNVisitor {
VL_DO_DANGLING(iterateChildren(nodep), nodep); // May delete nodep.
}
void visit(AstAssignW* nodep) override {
VL_RESTORER(m_assignwp);
VL_RESTORER(m_timingControlp);
m_assignwp = nodep;
m_timingControlp = nodep->timingControlp();
VL_DO_DANGLING(iterateChildren(nodep), nodep); // May delete nodep.
}

2
src/V3Width.cpp
View File

@ -1483,7 +1483,7 @@ class WidthVisitor final : public VNVisitor {
pushDeletep(nodep->unlinkFrBack());
return;
}
nodep->replaceWith(newp);
nodep->replaceWith(new AstAlways{newp});
VL_DO_DANGLING(pushDeletep(nodep), nodep);
}

176
src/verilog.y
View File

@ -46,23 +46,31 @@
MINTYPMAXDLY, \
"Unsupported: minimum/typical/maximum delay expressions. Using the typical delay"); \
}
// Given a list of assignments, if there is a delay add it to each assignment
#define DELAY_LIST(delayp, assignsp) \
if (delayp) { \
for (auto* nodep = assignsp; nodep; nodep = nodep->nextp()) { \
if (VN_IS(nodep, Implicit)) continue; \
auto* const assignp = VN_AS(nodep, NodeAssign); \
assignp->timingControlp(nodep == assignsp ? delayp : delayp->cloneTree(false)); \
} \
if (!delayp->backp()) delayp->deleteTree(); \
// Apply a delay to all continuous assignments under listp
static void DELAY_LIST(AstNode* listp, AstDelay* delayp) {
if (!delayp) return;
for (AstNode* nodep = listp; nodep; nodep = nodep->nextp()) {
if (VN_IS(nodep, Implicit)) continue;
AstAlways* const alwaysp = VN_AS(nodep, Always);
AstAssignW* const assignp = VN_AS(alwaysp->stmtsp(), AssignW);
assignp->timingControlp(delayp->backp() ? delayp->cloneTree(false) : delayp);
}
#define STRENGTHUNSUP(nodep) \
{ \
if (nodep) { \
BBUNSUP((nodep->fileline()), "Unsupported: Strength specifier on this gate type"); \
nodep->deleteTree(); \
} \
}
// Apply a strength to all continuous assignments under listp
static void STRENGTH_LIST(AstNode* listp, AstStrengthSpec* specp) {
if (!specp) return;
for (AstNode* nodep = listp; nodep; nodep = nodep->nextp()) {
if (VN_IS(nodep, Implicit)) continue;
AstAlways* const alwaysp = VN_AS(nodep, Always);
AstAssignW* const assignp = VN_AS(alwaysp->stmtsp(), AssignW);
assignp->strengthSpecp(specp->backp() ? specp->cloneTree(false) : specp);
}
}
static void STRENGTHUNSUP(AstStrengthSpec* nodep) {
if (!nodep) return;
BBUNSUP((nodep->fileline()), "Unsupported: Strength specifier on this gate type");
nodep->deleteTree();
}
//======================================================================
// Statics (for here only)
@ -133,19 +141,6 @@ const VBasicDTypeKwd LOGIC_IMPLICIT = VBasicDTypeKwd::LOGIC_IMPLICIT;
if (nodep) nodep->deleteTree(); \
}
// Apply a strength to a list of nodes under beginp
#define STRENGTH_LIST(beginp, strengthSpecNodep, typeToCast) \
{ \
if (AstStrengthSpec* const specp = VN_CAST(strengthSpecNodep, StrengthSpec)) { \
for (auto* nodep = beginp; nodep; nodep = nodep->nextp()) { \
if (VN_IS(nodep, Implicit)) continue; \
auto* const assignp = VN_AS(nodep, typeToCast); \
assignp->strengthSpecp(nodep == beginp ? specp : specp->cloneTree(false)); \
} \
if (!strengthSpecNodep->backp()) strengthSpecNodep->deleteTree(); \
} \
}
static void ERRSVKWD(FileLine* fileline, const string& tokname) {
static int toldonce = 0;
fileline->v3error(
@ -1802,8 +1797,7 @@ net_declaration<nodep>: // IEEE: net_declaration - excluding implict
net_declarationFront: // IEEE: beginning of net_declaration
net_declRESET net_type driveStrengthE net_scalaredE net_dataTypeE
{ VARDTYPE_NDECL($5);
GRAMMARP->setNetStrength(VN_CAST($3, StrengthSpec));
}
GRAMMARP->setNetStrength($3); }
| net_declRESET yINTERCONNECT signingE rangeListE
{ BBUNSUP($<fl>2, "Unsupported: interconnect");
VARDECL(WIRE);
@ -2634,8 +2628,8 @@ always_construct<nodep>: // IEEE: == always_construct
continuous_assign<nodep>: // IEEE: continuous_assign
yASSIGN driveStrengthE delay_controlE assignList ';'
{ $$ = $4;
STRENGTH_LIST($4, $2, AssignW);
DELAY_LIST($3, $4); }
STRENGTH_LIST($4, $2);
DELAY_LIST($4, $3); }
;
initial_construct<nodep>: // IEEE: initial_construct
@ -2913,13 +2907,14 @@ c_case_generate_item<genCaseItemp>: // IEEE: case_generate_item (for checkers)
//************************************************
// Assignments and register declarations
assignList<nodep>:
assignList<alwaysp>:
assignOne { $$ = $1; }
| assignList ',' assignOne { $$ = $1->addNext($3); }
;
assignOne<nodep>:
variable_lvalue '=' expr { $$ = new AstAssignW{$2, $1, $3}; }
assignOne<alwaysp>:
variable_lvalue '=' expr { AstAssignW* const ap = new AstAssignW{$2, $1, $3};
$$ = new AstAlways{ap}; }
;
delay_or_event_controlE<nodep>: // IEEE: delay_or_event_control plus empty
@ -2981,7 +2976,7 @@ netSig<varp>: // IEEE: net_decl_assignment - one element from
AstDelay* const delayp = $$->delayp() ? $$->delayp()->unlinkFrBack() : nullptr;
AstAssignW* const assignp = new AstAssignW{$4, new AstParseRef{$<fl>1, *$1}, $5, delayp};
if (GRAMMARP->m_netStrengthp) assignp->strengthSpecp(GRAMMARP->m_netStrengthp->cloneTree(false));
AstNode::addNext<AstNode, AstNode>($$, assignp); }
AstNode::addNext<AstNode, AstNode>($$, new AstAlways{assignp}); }
;
netId<strp>:
@ -5409,22 +5404,22 @@ let_port_item<varp>: // IEEE: let_port_Item
// Gate declarations
gateDecl<nodep>:
yBUF driveStrengthE delay_controlE gateBufList ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($3, $4); }
| yBUFIF0 driveStrengthE delay_controlE gateBufif0List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($3, $4); }
| yBUFIF1 driveStrengthE delay_controlE gateBufif1List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($3, $4); }
| yNOT driveStrengthE delay_controlE gateNotList ';' { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
| yNOTIF0 driveStrengthE delay_controlE gateNotif0List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($3, $4); }
| yNOTIF1 driveStrengthE delay_controlE gateNotif1List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($3, $4); }
| yAND driveStrengthE delay_controlE gateAndList ';' { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
| yNAND driveStrengthE delay_controlE gateNandList ';' { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
| yOR driveStrengthE delay_controlE gateOrList ';' { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
| yNOR driveStrengthE delay_controlE gateNorList ';' { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
| yXOR driveStrengthE delay_controlE gateXorList ';' { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
| yXNOR driveStrengthE delay_controlE gateXnorList ';' { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
| yPULLDOWN pulldown_strengthE delay_controlE gatePulldownList ';' { $$ = $4; DELAY_LIST($3, $4); }
| yPULLUP pullup_strengthE delay_controlE gatePullupList ';' { $$ = $4; DELAY_LIST($3, $4); }
| yNMOS delay_controlE gateBufif1List ';' { $$ = $3; DELAY_LIST($2, $3); }
| yPMOS delay_controlE gateBufif0List ';' { $$ = $3; DELAY_LIST($2, $3); }
yBUF driveStrengthE delay_controlE gateBufList ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($4, $3); }
| yBUFIF0 driveStrengthE delay_controlE gateBufif0List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($4, $3); }
| yBUFIF1 driveStrengthE delay_controlE gateBufif1List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($4, $3); }
| yNOT driveStrengthE delay_controlE gateNotList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yNOTIF0 driveStrengthE delay_controlE gateNotif0List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($4, $3); }
| yNOTIF1 driveStrengthE delay_controlE gateNotif1List ';' { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($4, $3); }
| yAND driveStrengthE delay_controlE gateAndList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yNAND driveStrengthE delay_controlE gateNandList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yOR driveStrengthE delay_controlE gateOrList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yNOR driveStrengthE delay_controlE gateNorList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yXOR driveStrengthE delay_controlE gateXorList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yXNOR driveStrengthE delay_controlE gateXnorList ';' { $$ = $4; STRENGTH_LIST($4, $2); DELAY_LIST($4, $3); }
| yPULLDOWN pulldown_strengthE delay_controlE gatePulldownList ';' { $$ = $4; DELAY_LIST($4, $3); }
| yPULLUP pullup_strengthE delay_controlE gatePullupList ';' { $$ = $4; DELAY_LIST($4, $3); }
| yNMOS delay_controlE gateBufif1List ';' { $$ = $3; DELAY_LIST($3, $2); }
| yPMOS delay_controlE gateBufif0List ';' { $$ = $3; DELAY_LIST($3, $2); }
//
| yTRAN delay_controlE gateUnsupList ';' { $$ = $3; GATEUNSUP($3, "tran"); }
| yRCMOS delay_controlE gateUnsupList ';' { $$ = $3; GATEUNSUP($3, "rcmos"); }
@ -5508,10 +5503,13 @@ gateBuf<nodep>:
{ AstNodeExpr* inp = $4;
while (inp->nextp()) inp = VN_AS(inp->nextp(), NodeExpr);
$$ = new AstImplicit{$<fl>1, inp->cloneTree(false)};
$$->addNext(new AstAssignW{$<fl>1, $2, GRAMMARP->createGatePin(inp->cloneTree(false))});
AstNodeExpr* const rhsp = GRAMMARP->createGatePin(inp->cloneTree(false));
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
for (AstNodeExpr* outp = $4; outp->nextp(); outp = VN_CAST(outp->nextp(), NodeExpr)) {
$$->addNext(new AstAssignW{$<fl>1, outp->cloneTree(false),
GRAMMARP->createGatePin(inp->cloneTree(false))});
AstNodeExpr* const rhsp = GRAMMARP->createGatePin(inp->cloneTree(false));
AstAssignW* const ap = new AstAssignW{$<fl>1, outp->cloneTree(false), rhsp};
$$->addNext(new AstAlways{ap});
}
DEL($1); DEL($4); }
;
@ -5520,69 +5518,99 @@ gateNot<nodep>:
{ AstNodeExpr* inp = $4;
while (inp->nextp()) inp = VN_AS(inp->nextp(), NodeExpr);
$$ = new AstImplicit{$<fl>1, inp->cloneTree(false)};
$$->addNext(new AstAssignW{$<fl>1, $2, new AstNot{$<fl>1,
GRAMMARP->createGatePin(inp->cloneTree(false))}});
AstNodeExpr* const rhsp = new AstNot{$<fl>1, GRAMMARP->createGatePin(inp->cloneTree(false))};
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
for (AstNodeExpr* outp = $4; outp->nextp(); outp = VN_CAST(outp->nextp(), NodeExpr)) {
$$->addNext(new AstAssignW{$<fl>1, outp->cloneTree(false),
new AstNot{$<fl>1,
GRAMMARP->createGatePin(inp->cloneTree(false))}});
AstNodeExpr* const rhsp = new AstNot{$<fl>1, GRAMMARP->createGatePin(inp->cloneTree(false))};
AstAssignW* const ap = new AstAssignW{$<fl>1, outp->cloneTree(false), rhsp};
$$->addNext(new AstAlways{ap});
}
DEL($1); DEL($4); }
DEL($1, $4); }
;
gateBufif0<nodep>:
gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
{ $$ = new AstImplicit{$<fl>1, $6->cloneTree(false)};
$<implicitp>$->addExprsp($4->cloneTree(false));
$$->addNext(new AstAssignW{$<fl>1, $2, new AstBufIf1{$<fl>1, new AstNot{$<fl>1, $6}, $4}}); DEL($1); }
AstNodeExpr* const rhsp = new AstBufIf1{$<fl>1, new AstNot{$<fl>1, $6}, $4};
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
DEL($1); }
;
gateBufif1<nodep>:
gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
{ $$ = new AstImplicit{$<fl>1, $6->cloneTree(false)};
$<implicitp>$->addExprsp($4->cloneTree(false));
$$->addNext(new AstAssignW{$<fl>1, $2, new AstBufIf1{$<fl>1, $6, $4}}); DEL($1); }
AstNodeExpr* const rhsp = new AstBufIf1{$<fl>1, $6, $4};
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
DEL($1); }
;
gateNotif0<nodep>:
gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
{ $$ = new AstImplicit{$<fl>1, $6->cloneTree(false)};
$<implicitp>$->addExprsp($4->cloneTree(false));
$$->addNext(new AstAssignW{$<fl>1, $2, new AstBufIf1{$<fl>1, new AstNot{$<fl>1, $6},
new AstNot{$<fl>1, $4}}}); DEL($1); }
AstNodeExpr* const rhsp = new AstBufIf1{$<fl>1, new AstNot{$<fl>1, $6}, new AstNot{$<fl>1, $4}};
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
DEL($1); }
;
gateNotif1<nodep>:
gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
{ $$ = new AstImplicit{$<fl>1, $6->cloneTree(false)};
$<implicitp>$->addExprsp($4->cloneTree(false));
$$->addNext(new AstAssignW{$<fl>1, $2, new AstBufIf1{$<fl>1, $6, new AstNot{$<fl>1, $4}}}); DEL($1); }
AstNodeExpr* const rhsp = new AstBufIf1{$<fl>1, $6, new AstNot{$<fl>1, $4}};
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
DEL($1); }
;
gateAnd<nodep>:
gateFront variable_lvalue ',' gateAndPinList ')'
{ $$ = new AstImplicit{$<fl>1, $4->cloneTree(false)};
$$->addNext(new AstAssignW{$<fl>1, $2, $4}); DEL($1); }
AstNodeExpr* const rhsp = $4;
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
DEL($1); }
;
gateNand<nodep>:
gateFront variable_lvalue ',' gateAndPinList ')'
{ $$ = new AstImplicit{$<fl>1, $4->cloneTree(false)};
$$->addNext(new AstAssignW{$<fl>1, $2, new AstNot{$<fl>1, $4}}); DEL($1); }
AstNodeExpr* const rhsp = new AstNot{$<fl>1, $4};
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
DEL($1); }
;
gateOr<nodep>:
gateFront variable_lvalue ',' gateOrPinList ')'
{ $$ = new AstImplicit{$<fl>1, $4->cloneTree(false)};
$$->addNext(new AstAssignW{$<fl>1, $2, $4}); DEL($1); }
AstNodeExpr* const rhsp = $4;
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
DEL($1); }
;
gateNor<nodep>:
gateFront variable_lvalue ',' gateOrPinList ')'
{ $$ = new AstImplicit{$<fl>1, $4->cloneTree(false)};
$$->addNext(new AstAssignW{$<fl>1, $2, new AstNot{$<fl>1, $4}}); DEL($1); }
AstNodeExpr* const rhsp = new AstNot{$<fl>1, $4};
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
DEL($1); }
;
gateXor<nodep>:
gateFront variable_lvalue ',' gateXorPinList ')'
{ $$ = new AstImplicit{$<fl>1, $4->cloneTree(false)};
$$->addNext(new AstAssignW{$<fl>1, $2, $4}); DEL($1); }
AstNodeExpr* const rhsp = $4;
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
DEL($1); }
;
gateXnor<nodep>:
gateFront variable_lvalue ',' gateXorPinList ')'
{ $$ = new AstImplicit{$<fl>1, $4->cloneTree(false)};
$$->addNext(new AstAssignW{$<fl>1, $2, new AstNot{$<fl>1, $4}}); DEL($1); }
AstNodeExpr* const rhsp = new AstNot{$<fl>1, $4};
AstAssignW* const ap = new AstAssignW{$<fl>1, $2, rhsp};
$$->addNext(new AstAlways{ap});
DEL($1); }
;
gatePullup<nodep>:
gateFront variable_lvalue ')' { $$ = new AstPull{$<fl>1, $2, true}; DEL($1); }
@ -5634,12 +5662,12 @@ strength1<strength>:
| yWEAK1 { $$ = VStrength::WEAK; }
;
driveStrengthE<nodep>:
driveStrengthE<strengthSpecp>:
/* empty */ { $$ = nullptr; }
| driveStrength { $$ = $1; }
;
driveStrength<nodep>:
driveStrength<strengthSpecp>:
yP_PAR__STRENGTH strength0 ',' strength1 ')' { $$ = new AstStrengthSpec{$1, $2, $4}; }
| yP_PAR__STRENGTH strength1 ',' strength0 ')' { $$ = new AstStrengthSpec{$1, $4, $2}; }
| yP_PAR__STRENGTH strength0 ',' yHIGHZ1 ')' { $$ = nullptr; BBUNSUP($<fl>4, "Unsupported: highz strength"); }

1362
test_regress/t/t_dump_json.out
View File

File diff suppressed because it is too large Load Diff

2
test_regress/t/t_gate_chained.py
View File

@ -48,6 +48,6 @@ test.compile(
test.execute()
# Must be <<9000 above to prove this worked
test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 8575)
test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 8554)
test.passes()

49
test_regress/t/t_json_only_first.out
View File

@ -42,61 +42,64 @@
{"type":"VAR","name":"clk","addr":"(FB)","loc":"d,48:10,48:13","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"d","addr":"(Z)","loc":"d,49:16,49:17","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"q","addr":"(CB)","loc":"d,50:22,50:23","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"ASSIGNW","name":"","addr":"(HB)","loc":"d,53:13,53:14","dtypep":"(G)",
"rhsp": [
{"type":"VARREF","name":"d","addr":"(IB)","loc":"d,49:16,49:17","dtypep":"(G)","access":"RD","varp":"(Z)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"q","addr":"(JB)","loc":"d,53:13,53:14","dtypep":"(G)","access":"WR","varp":"(CB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
{"type":"ALWAYS","name":"","addr":"(HB)","loc":"d,53:13,53:14","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(IB)","loc":"d,53:13,53:14","dtypep":"(G)",
"rhsp": [
{"type":"VARREF","name":"d","addr":"(JB)","loc":"d,49:16,49:17","dtypep":"(G)","access":"RD","varp":"(Z)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"q","addr":"(KB)","loc":"d,53:13,53:14","dtypep":"(G)","access":"WR","varp":"(CB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]}
]},
{"type":"MODULE","name":"mod1__W4","addr":"(M)","loc":"d,31:8,31:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mod1","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"WIDTH","addr":"(KB)","loc":"d,32:15,32:20","dtypep":"(LB)","origName":"WIDTH","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":true,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],
{"type":"VAR","name":"WIDTH","addr":"(LB)","loc":"d,32:15,32:20","dtypep":"(MB)","origName":"WIDTH","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":true,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],
"valuep": [
{"type":"CONST","name":"32'sh4","addr":"(MB)","loc":"d,19:18,19:19","dtypep":"(LB)"}
{"type":"CONST","name":"32'sh4","addr":"(NB)","loc":"d,19:18,19:19","dtypep":"(MB)"}
],"attrsp": []},
{"type":"VAR","name":"clk","addr":"(R)","loc":"d,34:24,34:27","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"d","addr":"(U)","loc":"d,35:30,35:31","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"q","addr":"(O)","loc":"d,36:30,36:31","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"IGNORED","addr":"(NB)","loc":"d,39:15,39:22","dtypep":"(LB)","origName":"IGNORED","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],
{"type":"VAR","name":"IGNORED","addr":"(OB)","loc":"d,39:15,39:22","dtypep":"(MB)","origName":"IGNORED","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],
"valuep": [
{"type":"CONST","name":"32'sh1","addr":"(OB)","loc":"d,39:25,39:26","dtypep":"(LB)"}
{"type":"CONST","name":"32'sh1","addr":"(PB)","loc":"d,39:25,39:26","dtypep":"(MB)"}
],"attrsp": []},
{"type":"ALWAYS","name":"","addr":"(PB)","loc":"d,41:4,41:10","keyword":"always","isSuspendable":false,"needProcess":false,
{"type":"ALWAYS","name":"","addr":"(QB)","loc":"d,41:4,41:10","keyword":"always","isSuspendable":false,"needProcess":false,
"sentreep": [
{"type":"SENTREE","name":"","addr":"(QB)","loc":"d,41:11,41:12","isMulti":false,
{"type":"SENTREE","name":"","addr":"(RB)","loc":"d,41:11,41:12","isMulti":false,
"sensesp": [
{"type":"SENITEM","name":"","addr":"(RB)","loc":"d,41:13,41:20","edgeType":"POS",
{"type":"SENITEM","name":"","addr":"(SB)","loc":"d,41:13,41:20","edgeType":"POS",
"sensp": [
{"type":"VARREF","name":"clk","addr":"(SB)","loc":"d,41:21,41:24","dtypep":"(I)","access":"RD","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"clk","addr":"(TB)","loc":"d,41:21,41:24","dtypep":"(I)","access":"RD","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],"condp": []}
]}
],
"stmtsp": [
{"type":"ASSIGNDLY","name":"","addr":"(TB)","loc":"d,42:8,42:10","dtypep":"(G)",
{"type":"ASSIGNDLY","name":"","addr":"(UB)","loc":"d,42:8,42:10","dtypep":"(G)",
"rhsp": [
{"type":"VARREF","name":"d","addr":"(UB)","loc":"d,42:11,42:12","dtypep":"(G)","access":"RD","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"d","addr":"(VB)","loc":"d,42:11,42:12","dtypep":"(G)","access":"RD","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"q","addr":"(VB)","loc":"d,42:6,42:7","dtypep":"(G)","access":"WR","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"q","addr":"(WB)","loc":"d,42:6,42:7","dtypep":"(G)","access":"WR","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],"timingControlp": []}
]}
]}
],"filesp": [],
"miscsp": [
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(WB)",
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(XB)",
"typesp": [
{"type":"BASICDTYPE","name":"logic","addr":"(I)","loc":"d,34:24,34:27","dtypep":"(I)","keyword":"logic","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,15:16,15:17","dtypep":"(G)","keyword":"logic","range":"3:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(LB)","loc":"d,19:18,19:19","dtypep":"(LB)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"VOIDDTYPE","name":"","addr":"(WB)","loc":"a,0:0,0:0","dtypep":"(WB)","generic":false}
{"type":"BASICDTYPE","name":"logic","addr":"(MB)","loc":"d,19:18,19:19","dtypep":"(MB)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"VOIDDTYPE","name":"","addr":"(XB)","loc":"a,0:0,0:0","dtypep":"(XB)","generic":false}
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(XB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(YB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(YB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(XB)","varsp": [],"blocksp": [],"inlinesp": []}
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(ZB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(YB)","varsp": [],"blocksp": [],"inlinesp": []}
]}
]}
]}

214
test_regress/t/t_json_only_flat.out
View File

@ -31,125 +31,155 @@
{"type":"VARSCOPE","name":"clk","addr":"(CB)","loc":"d,13:10,13:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(I)"},
{"type":"VARSCOPE","name":"d","addr":"(DB)","loc":"d,14:16,14:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(K)"},
{"type":"VARSCOPE","name":"t.q","addr":"(EB)","loc":"d,15:22,15:23","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(L)"},
{"type":"ASSIGNW","name":"","addr":"(FB)","loc":"d,15:22,15:23","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"q","addr":"(GB)","loc":"d,15:22,15:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.q","addr":"(HB)","loc":"d,15:22,15:23","dtypep":"(H)","access":"WR","varp":"(L)","varScopep":"(EB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"t.clk","addr":"(IB)","loc":"d,13:10,13:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(M)"},
{"type":"ASSIGNW","name":"","addr":"(JB)","loc":"d,13:10,13:13","dtypep":"(J)",
"rhsp": [
{"type":"VARREF","name":"clk","addr":"(KB)","loc":"d,13:10,13:13","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.clk","addr":"(LB)","loc":"d,13:10,13:13","dtypep":"(J)","access":"WR","varp":"(M)","varScopep":"(IB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"t.d","addr":"(MB)","loc":"d,14:16,14:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(N)"},
{"type":"ASSIGNW","name":"","addr":"(NB)","loc":"d,14:16,14:17","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"d","addr":"(OB)","loc":"d,14:16,14:17","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.d","addr":"(PB)","loc":"d,14:16,14:17","dtypep":"(H)","access":"WR","varp":"(N)","varScopep":"(MB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"t.between","addr":"(QB)","loc":"d,17:22,17:29","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(O)"},
{"type":"VARSCOPE","name":"t.cell1.WIDTH","addr":"(RB)","loc":"d,32:15,32:20","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(P)"},
{"type":"VARSCOPE","name":"t.cell1.clk","addr":"(SB)","loc":"d,34:24,34:27","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(S)"},
{"type":"ASSIGNW","name":"","addr":"(TB)","loc":"d,34:24,34:27","dtypep":"(J)",
"rhsp": [
{"type":"VARREF","name":"clk","addr":"(UB)","loc":"d,34:24,34:27","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell1.clk","addr":"(VB)","loc":"d,34:24,34:27","dtypep":"(J)","access":"WR","varp":"(S)","varScopep":"(SB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"t.cell1.d","addr":"(WB)","loc":"d,35:30,35:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(T)"},
{"type":"ASSIGNW","name":"","addr":"(XB)","loc":"d,35:30,35:31","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"d","addr":"(YB)","loc":"d,35:30,35:31","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell1.d","addr":"(ZB)","loc":"d,35:30,35:31","dtypep":"(H)","access":"WR","varp":"(T)","varScopep":"(WB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"t.cell1.q","addr":"(AC)","loc":"d,36:30,36:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(U)"},
{"type":"ASSIGNW","name":"","addr":"(BC)","loc":"d,36:30,36:31","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"t.between","addr":"(CC)","loc":"d,36:30,36:31","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(QB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell1.q","addr":"(DC)","loc":"d,36:30,36:31","dtypep":"(H)","access":"WR","varp":"(U)","varScopep":"(AC)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"t.cell1.IGNORED","addr":"(EC)","loc":"d,39:15,39:22","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(V)"},
{"type":"VARSCOPE","name":"t.cell2.clk","addr":"(FC)","loc":"d,48:10,48:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(X)"},
{"type":"ASSIGNW","name":"","addr":"(GC)","loc":"d,48:10,48:13","dtypep":"(J)",
"rhsp": [
{"type":"VARREF","name":"clk","addr":"(HC)","loc":"d,48:10,48:13","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell2.clk","addr":"(IC)","loc":"d,48:10,48:13","dtypep":"(J)","access":"WR","varp":"(X)","varScopep":"(FC)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"t.cell2.d","addr":"(JC)","loc":"d,49:16,49:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Y)"},
{"type":"ASSIGNW","name":"","addr":"(KC)","loc":"d,49:16,49:17","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"t.between","addr":"(LC)","loc":"d,49:16,49:17","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(QB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell2.d","addr":"(MC)","loc":"d,49:16,49:17","dtypep":"(H)","access":"WR","varp":"(Y)","varScopep":"(JC)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"t.cell2.q","addr":"(NC)","loc":"d,50:22,50:23","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Z)"},
{"type":"ASSIGNW","name":"","addr":"(OC)","loc":"d,50:22,50:23","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"q","addr":"(PC)","loc":"d,50:22,50:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell2.q","addr":"(QC)","loc":"d,50:22,50:23","dtypep":"(H)","access":"WR","varp":"(Z)","varScopep":"(NC)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
{"type":"ALWAYS","name":"","addr":"(FB)","loc":"d,15:22,15:23","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(GB)","loc":"d,15:22,15:23","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"q","addr":"(HB)","loc":"d,15:22,15:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.q","addr":"(IB)","loc":"d,15:22,15:23","dtypep":"(H)","access":"WR","varp":"(L)","varScopep":"(EB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"t.clk","addr":"(JB)","loc":"d,13:10,13:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(M)"},
{"type":"ALWAYS","name":"","addr":"(KB)","loc":"d,13:10,13:13","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(LB)","loc":"d,13:10,13:13","dtypep":"(J)",
"rhsp": [
{"type":"VARREF","name":"clk","addr":"(MB)","loc":"d,13:10,13:13","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.clk","addr":"(NB)","loc":"d,13:10,13:13","dtypep":"(J)","access":"WR","varp":"(M)","varScopep":"(JB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"t.d","addr":"(OB)","loc":"d,14:16,14:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(N)"},
{"type":"ALWAYS","name":"","addr":"(PB)","loc":"d,14:16,14:17","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(QB)","loc":"d,14:16,14:17","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"d","addr":"(RB)","loc":"d,14:16,14:17","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.d","addr":"(SB)","loc":"d,14:16,14:17","dtypep":"(H)","access":"WR","varp":"(N)","varScopep":"(OB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"t.between","addr":"(TB)","loc":"d,17:22,17:29","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(O)"},
{"type":"VARSCOPE","name":"t.cell1.WIDTH","addr":"(UB)","loc":"d,32:15,32:20","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(P)"},
{"type":"VARSCOPE","name":"t.cell1.clk","addr":"(VB)","loc":"d,34:24,34:27","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(S)"},
{"type":"ALWAYS","name":"","addr":"(WB)","loc":"d,34:24,34:27","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(XB)","loc":"d,34:24,34:27","dtypep":"(J)",
"rhsp": [
{"type":"VARREF","name":"clk","addr":"(YB)","loc":"d,34:24,34:27","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell1.clk","addr":"(ZB)","loc":"d,34:24,34:27","dtypep":"(J)","access":"WR","varp":"(S)","varScopep":"(VB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"t.cell1.d","addr":"(AC)","loc":"d,35:30,35:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(T)"},
{"type":"ALWAYS","name":"","addr":"(BC)","loc":"d,35:30,35:31","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(CC)","loc":"d,35:30,35:31","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"d","addr":"(DC)","loc":"d,35:30,35:31","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell1.d","addr":"(EC)","loc":"d,35:30,35:31","dtypep":"(H)","access":"WR","varp":"(T)","varScopep":"(AC)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"t.cell1.q","addr":"(FC)","loc":"d,36:30,36:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(U)"},
{"type":"ALWAYS","name":"","addr":"(GC)","loc":"d,36:30,36:31","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(HC)","loc":"d,36:30,36:31","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"t.between","addr":"(IC)","loc":"d,36:30,36:31","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell1.q","addr":"(JC)","loc":"d,36:30,36:31","dtypep":"(H)","access":"WR","varp":"(U)","varScopep":"(FC)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"t.cell1.IGNORED","addr":"(KC)","loc":"d,39:15,39:22","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(V)"},
{"type":"VARSCOPE","name":"t.cell2.clk","addr":"(LC)","loc":"d,48:10,48:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(X)"},
{"type":"ALWAYS","name":"","addr":"(MC)","loc":"d,48:10,48:13","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(NC)","loc":"d,48:10,48:13","dtypep":"(J)",
"rhsp": [
{"type":"VARREF","name":"clk","addr":"(OC)","loc":"d,48:10,48:13","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell2.clk","addr":"(PC)","loc":"d,48:10,48:13","dtypep":"(J)","access":"WR","varp":"(X)","varScopep":"(LC)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"t.cell2.d","addr":"(QC)","loc":"d,49:16,49:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Y)"},
{"type":"ALWAYS","name":"","addr":"(RC)","loc":"d,49:16,49:17","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(SC)","loc":"d,49:16,49:17","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"t.between","addr":"(TC)","loc":"d,49:16,49:17","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell2.d","addr":"(UC)","loc":"d,49:16,49:17","dtypep":"(H)","access":"WR","varp":"(Y)","varScopep":"(QC)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"t.cell2.q","addr":"(VC)","loc":"d,50:22,50:23","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Z)"},
{"type":"ALWAYS","name":"","addr":"(WC)","loc":"d,50:22,50:23","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(XC)","loc":"d,50:22,50:23","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"q","addr":"(YC)","loc":"d,50:22,50:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.cell2.q","addr":"(ZC)","loc":"d,50:22,50:23","dtypep":"(H)","access":"WR","varp":"(Z)","varScopep":"(VC)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]}
],
"blocksp": [
{"type":"ALWAYS","name":"","addr":"(RC)","loc":"d,41:4,41:10","keyword":"always","isSuspendable":false,"needProcess":false,
{"type":"ALWAYS","name":"","addr":"(AD)","loc":"d,41:4,41:10","keyword":"always","isSuspendable":false,"needProcess":false,
"sentreep": [
{"type":"SENTREE","name":"","addr":"(SC)","loc":"d,41:11,41:12","isMulti":false,
{"type":"SENTREE","name":"","addr":"(BD)","loc":"d,41:11,41:12","isMulti":false,
"sensesp": [
{"type":"SENITEM","name":"","addr":"(TC)","loc":"d,41:13,41:20","edgeType":"POS",
{"type":"SENITEM","name":"","addr":"(CD)","loc":"d,41:13,41:20","edgeType":"POS",
"sensp": [
{"type":"VARREF","name":"clk","addr":"(UC)","loc":"d,41:21,41:24","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"clk","addr":"(DD)","loc":"d,41:21,41:24","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"}
],"condp": []}
]}
],
"stmtsp": [
{"type":"ASSIGNDLY","name":"","addr":"(VC)","loc":"d,42:8,42:10","dtypep":"(H)",
{"type":"ASSIGNDLY","name":"","addr":"(ED)","loc":"d,42:8,42:10","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"d","addr":"(WC)","loc":"d,42:11,42:12","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"d","addr":"(FD)","loc":"d,42:11,42:12","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"t.between","addr":"(XC)","loc":"d,42:6,42:7","dtypep":"(H)","access":"WR","varp":"(O)","varScopep":"(QB)","classOrPackagep":"UNLINKED"}
{"type":"VARREF","name":"t.between","addr":"(GD)","loc":"d,42:6,42:7","dtypep":"(H)","access":"WR","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"}
],"timingControlp": []}
]},
{"type":"ASSIGNW","name":"","addr":"(YC)","loc":"d,53:13,53:14","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"t.between","addr":"(ZC)","loc":"d,17:22,17:29","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(QB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"q","addr":"(AD)","loc":"d,53:13,53:14","dtypep":"(H)","access":"WR","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
{"type":"ALWAYS","name":"","addr":"(HD)","loc":"d,53:13,53:14","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(ID)","loc":"d,53:13,53:14","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"t.between","addr":"(JD)","loc":"d,17:22,17:29","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"q","addr":"(KD)","loc":"d,53:13,53:14","dtypep":"(H)","access":"WR","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]}
],"inlinesp": []}
]}
]}
],"filesp": [],
"miscsp": [
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(BD)",
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(LD)",
"typesp": [
{"type":"BASICDTYPE","name":"logic","addr":"(J)","loc":"d,34:24,34:27","dtypep":"(J)","keyword":"logic","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,15:16,15:17","dtypep":"(H)","keyword":"logic","range":"3:0","generic":true,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(Q)","loc":"d,19:18,19:19","dtypep":"(Q)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"VOIDDTYPE","name":"","addr":"(BD)","loc":"a,0:0,0:0","dtypep":"(BD)","generic":false}
{"type":"VOIDDTYPE","name":"","addr":"(LD)","loc":"a,0:0,0:0","dtypep":"(LD)","generic":false}
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(CD)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(MD)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(DD)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(CD)","varsp": [],"blocksp": [],"inlinesp": []}
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(ND)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(MD)","varsp": [],"blocksp": [],"inlinesp": []}
]}
]}
]}

40
test_regress/t/t_json_only_flat_no_inline_mod.out
View File

@ -11,21 +11,27 @@
"varsp": [
{"type":"VARSCOPE","name":"i_clk","addr":"(L)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(G)"},
{"type":"VARSCOPE","name":"top.i_clk","addr":"(M)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(I)"},
{"type":"ASSIGNW","name":"","addr":"(N)","loc":"d,11:24,11:29","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_clk","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"top.i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(H)","access":"WR","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"top.f.i_clk","addr":"(Q)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"},
{"type":"ASSIGNW","name":"","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_clk","addr":"(S)","loc":"d,7:24,7:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"top.f.i_clk","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)","access":"WR","varp":"(J)","varScopep":"(Q)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
{"type":"ALWAYS","name":"","addr":"(N)","loc":"d,11:24,11:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"top.i_clk","addr":"(Q)","loc":"d,11:24,11:29","dtypep":"(H)","access":"WR","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"top.f.i_clk","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"},
{"type":"ALWAYS","name":"","addr":"(S)","loc":"d,7:24,7:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_clk","addr":"(U)","loc":"d,7:24,7:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"top.f.i_clk","addr":"(V)","loc":"d,7:24,7:29","dtypep":"(H)","access":"WR","varp":"(J)","varScopep":"(R)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]}
],"blocksp": [],"inlinesp": []}
]}
]}
@ -37,9 +43,9 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(U)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(W)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(V)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(U)","varsp": [],"blocksp": [],"inlinesp": []}
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(X)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(W)","varsp": [],"blocksp": [],"inlinesp": []}
]}
]}
]}

40
test_regress/t/t_json_only_flat_pub_mod.out
View File

@ -11,21 +11,27 @@
"varsp": [
{"type":"VARSCOPE","name":"i_clk","addr":"(L)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(G)"},
{"type":"VARSCOPE","name":"top.i_clk","addr":"(M)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(I)"},
{"type":"ASSIGNW","name":"","addr":"(N)","loc":"d,11:24,11:29","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_clk","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"top.i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(H)","access":"WR","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"top.f.i_clk","addr":"(Q)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"},
{"type":"ASSIGNW","name":"","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_clk","addr":"(S)","loc":"d,7:24,7:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"top.f.i_clk","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)","access":"WR","varp":"(J)","varScopep":"(Q)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
{"type":"ALWAYS","name":"","addr":"(N)","loc":"d,11:24,11:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"top.i_clk","addr":"(Q)","loc":"d,11:24,11:29","dtypep":"(H)","access":"WR","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]},
{"type":"VARSCOPE","name":"top.f.i_clk","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"},
{"type":"ALWAYS","name":"","addr":"(S)","loc":"d,7:24,7:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_clk","addr":"(U)","loc":"d,7:24,7:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"top.f.i_clk","addr":"(V)","loc":"d,7:24,7:29","dtypep":"(H)","access":"WR","varp":"(J)","varScopep":"(R)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]}
],"blocksp": [],"inlinesp": []}
]}
]}
@ -37,9 +43,9 @@
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(U)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(W)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(V)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(U)","varsp": [],"blocksp": [],"inlinesp": []}
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(X)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(W)","varsp": [],"blocksp": [],"inlinesp": []}
]}
]}
]}

304
test_regress/t/t_json_only_flat_vlvbound.out
View File

@ -19,296 +19,308 @@
{"type":"VARSCOPE","name":"o_a","addr":"(T)","loc":"d,11:25,11:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(J)"},
{"type":"VARSCOPE","name":"o_b","addr":"(U)","loc":"d,12:25,12:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(L)"},
{"type":"VARSCOPE","name":"vlvbound_test.i_a","addr":"(V)","loc":"d,9:25,9:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(M)"},
{"type":"ASSIGNW","name":"","addr":"(W)","loc":"d,9:25,9:28","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_a","addr":"(X)","loc":"d,9:25,9:28","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(R)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"vlvbound_test.i_a","addr":"(Y)","loc":"d,9:25,9:28","dtypep":"(H)","access":"WR","varp":"(M)","varScopep":"(V)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"vlvbound_test.i_b","addr":"(Z)","loc":"d,10:25,10:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(N)"},
{"type":"ASSIGNW","name":"","addr":"(AB)","loc":"d,10:25,10:28","dtypep":"(H)",
"rhsp": [
{"type":"VARREF","name":"i_b","addr":"(BB)","loc":"d,10:25,10:28","dtypep":"(H)","access":"RD","varp":"(I)","varScopep":"(S)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"vlvbound_test.i_b","addr":"(CB)","loc":"d,10:25,10:28","dtypep":"(H)","access":"WR","varp":"(N)","varScopep":"(Z)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"vlvbound_test.o_a","addr":"(DB)","loc":"d,11:25,11:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(O)"},
{"type":"ASSIGNW","name":"","addr":"(EB)","loc":"d,11:25,11:28","dtypep":"(K)",
"rhsp": [
{"type":"VARREF","name":"o_a","addr":"(FB)","loc":"d,11:25,11:28","dtypep":"(K)","access":"RD","varp":"(J)","varScopep":"(T)","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"vlvbound_test.o_a","addr":"(GB)","loc":"d,11:25,11:28","dtypep":"(K)","access":"WR","varp":"(O)","varScopep":"(DB)","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []},
{"type":"VARSCOPE","name":"vlvbound_test.o_b","addr":"(HB)","loc":"d,12:25,12:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(P)"},
{"type":"ASSIGNW","name":"","addr":"(IB)","loc":"d,12:25,12:28","dtypep":"(K)",
"rhsp": [
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{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(UB)","loc":"d,15:34,15:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(VB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(WB)","loc":"d,15:57,15:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(XB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(YB)","loc":"d,16:17,16:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(ZB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(AC)","loc":"d,17:13,17:14","dtypep":"(SB)","isTrace":true,"scopep":"(Q)","varp":"(BC)"}
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{"type":"ALWAYS","name":"","addr":"(BB)","loc":"d,10:25,10:28","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
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{"type":"ALWAYS","name":"","addr":"(GB)","loc":"d,11:25,11:28","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
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{"type":"ALWAYS","name":"","addr":"(LB)","loc":"d,12:25,12:28","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
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{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(RB)","loc":"d,15:57,15:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(SB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(TB)","loc":"d,16:17,16:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(UB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(VB)","loc":"d,17:13,17:14","dtypep":"(WB)","isTrace":true,"scopep":"(Q)","varp":"(XB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(YB)","loc":"d,15:34,15:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(ZB)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(AC)","loc":"d,15:57,15:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(BC)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(CC)","loc":"d,16:17,16:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(DC)"},
{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(EC)","loc":"d,17:13,17:14","dtypep":"(WB)","isTrace":true,"scopep":"(Q)","varp":"(FC)"}
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{"type":"ALWAYS","name":"","addr":"(GC)","loc":"d,24:14,24:15","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
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{"type":"ASSIGN","name":"","addr":"(IC)","loc":"d,24:20,24:23","dtypep":"(H)",
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{"type":"VARREF","name":"i_a","addr":"(JC)","loc":"d,24:20,24:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(R)","classOrPackagep":"UNLINKED"}
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{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(KC)","loc":"d,15:57,15:60","dtypep":"(H)","access":"WR","varp":"(SB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"}
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{"type":"CRESET","name":"","addr":"(LC)","loc":"d,16:17,16:20","constructing":false,
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{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(MC)","loc":"d,16:17,16:20","dtypep":"(K)","access":"WR","varp":"(UB)","varScopep":"(TB)","classOrPackagep":"UNLINKED"}
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{"type":"CONST","name":"32'sh0","addr":"(QC)","loc":"d,18:12,18:13","dtypep":"(RC)"}
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{"type":"CONST","name":"32'sh7","addr":"(XC)","loc":"d,18:20,18:21","dtypep":"(RC)"}
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{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(YC)","loc":"d,18:16,18:17","dtypep":"(WB)","access":"RD","varp":"(XB)","varScopep":"(VB)","classOrPackagep":"UNLINKED"}
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{"type":"CONST","name":"2'h0","addr":"(BD)","loc":"d,19:34,19:39","dtypep":"(CD)"}
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{"type":"SEL","name":"","addr":"(DD)","loc":"d,19:20,19:21","dtypep":"(CD)","widthConst":2,"declRange":"[15:0]","declElWidth":1,
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{"type":"SEL","name":"","addr":"(FD)","loc":"d,19:22,19:23","dtypep":"(GD)","widthConst":4,
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{"type":"SEL","name":"","addr":"(MD)","loc":"d,19:10,19:11","dtypep":"(WC)","widthConst":1,"declRange":"[6:0]","declElWidth":1,
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{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(ZD)","loc":"d,21:5,21:11","dtypep":"(K)","access":"WR","varp":"(QB)","varScopep":"(PB)","classOrPackagep":"UNLINKED"}
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{"type":"ALWAYS","name":"","addr":"(DE)","loc":"d,25:14,25:15","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
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{"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(ZB)","loc":"d,15:34,15:37","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__Vfuncout","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
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]}
]}
]}

83
test_regress/t/t_json_only_tag.out
View File

@ -10,35 +10,38 @@
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]}
@ -47,50 +50,50 @@
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{"type":"BASICDTYPE","name":"logic","addr":"(PB)","loc":"d,23:7,23:12","dtypep":"(PB)","keyword":"logic","generic":false,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(QB)","loc":"d,24:7,24:12","dtypep":"(QB)","keyword":"logic","generic":false,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(OB)","loc":"d,21:7,21:12","dtypep":"(OB)","keyword":"logic","generic":false,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(PB)","loc":"d,22:7,22:12","dtypep":"(PB)","keyword":"logic","generic":false,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(QB)","loc":"d,23:7,23:12","dtypep":"(QB)","keyword":"logic","generic":false,"rangep": []},
{"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,24:7,24:12","dtypep":"(RB)","keyword":"logic","generic":false,"rangep": []},
{"type":"STRUCTDTYPE","name":"m.my_struct","addr":"(K)","loc":"d,20:12,20:18","dtypep":"(K)","packed":true,"isFourstate":true,"generic":false,"classOrPackagep":"UNLINKED",
"membersp": [
{"type":"MEMBERDTYPE","name":"clk","addr":"(RB)","loc":"d,21:19,21:22","dtypep":"(NB)","isConstrainedRand":false,"name":"clk","tag":"this is clk","generic":false,"refDTypep":"(NB)","childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"k","addr":"(SB)","loc":"d,22:19,22:20","dtypep":"(OB)","isConstrainedRand":false,"name":"k","tag":"","generic":false,"refDTypep":"(OB)","childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"enable","addr":"(TB)","loc":"d,23:19,23:25","dtypep":"(PB)","isConstrainedRand":false,"name":"enable","tag":"enable","generic":false,"refDTypep":"(PB)","childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"data","addr":"(UB)","loc":"d,24:19,24:23","dtypep":"(QB)","isConstrainedRand":false,"name":"data","tag":"data","generic":false,"refDTypep":"(QB)","childDTypep": [],"valuep": []}
{"type":"MEMBERDTYPE","name":"clk","addr":"(SB)","loc":"d,21:19,21:22","dtypep":"(OB)","isConstrainedRand":false,"name":"clk","tag":"this is clk","generic":false,"refDTypep":"(OB)","childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"k","addr":"(TB)","loc":"d,22:19,22:20","dtypep":"(PB)","isConstrainedRand":false,"name":"k","tag":"","generic":false,"refDTypep":"(PB)","childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"enable","addr":"(UB)","loc":"d,23:19,23:25","dtypep":"(QB)","isConstrainedRand":false,"name":"enable","tag":"enable","generic":false,"refDTypep":"(QB)","childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"data","addr":"(VB)","loc":"d,24:19,24:23","dtypep":"(RB)","isConstrainedRand":false,"name":"data","tag":"data","generic":false,"refDTypep":"(RB)","childDTypep": [],"valuep": []}
]},
{"type":"IFACEREFDTYPE","name":"","addr":"(O)","loc":"d,29:8,29:12","dtypep":"(O)","isPortDecl":false,"isVirtual":false,"cellName":"itop","ifaceName":"ifc","modportName":"","generic":false,"ifacep":"UNLINKED","cellp":"(L)","modportp":"UNLINKED","paramsp": []},
{"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"d,31:27,31:28","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
{"type":"REFDTYPE","name":"my_struct","addr":"(VB)","loc":"d,31:4,31:13","dtypep":"(K)","generic":false,"typedefp":"UNLINKED","refDTypep":"(K)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []},
{"type":"UNPACKARRAYDTYPE","name":"","addr":"(Q)","loc":"d,31:26,31:27","dtypep":"(Q)","isCompound":false,"declRange":"[0:1]","generic":false,"refDTypep":"(VB)","childDTypep": [],
{"type":"REFDTYPE","name":"my_struct","addr":"(WB)","loc":"d,31:4,31:13","dtypep":"(K)","generic":false,"typedefp":"UNLINKED","refDTypep":"(K)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []},
{"type":"UNPACKARRAYDTYPE","name":"","addr":"(Q)","loc":"d,31:26,31:27","dtypep":"(Q)","isCompound":false,"declRange":"[0:1]","generic":false,"refDTypep":"(WB)","childDTypep": [],
"rangep": [
{"type":"RANGE","name":"","addr":"(WB)","loc":"d,31:26,31:27","ascending":true,"fromBracket":true,
{"type":"RANGE","name":"","addr":"(XB)","loc":"d,31:26,31:27","ascending":true,"fromBracket":true,
"leftp": [
{"type":"CONST","name":"32'h0","addr":"(XB)","loc":"d,31:27,31:28","dtypep":"(S)"}
{"type":"CONST","name":"32'h0","addr":"(YB)","loc":"d,31:27,31:28","dtypep":"(S)"}
],
"rightp": [
{"type":"CONST","name":"32'h1","addr":"(YB)","loc":"d,31:27,31:28","dtypep":"(S)"}
{"type":"CONST","name":"32'h1","addr":"(ZB)","loc":"d,31:27,31:28","dtypep":"(S)"}
]}
]},
{"type":"BASICDTYPE","name":"string","addr":"(AB)","loc":"d,35:26,35:32","dtypep":"(AB)","keyword":"string","generic":true,"rangep": []}
{"type":"BASICDTYPE","name":"string","addr":"(BB)","loc":"d,35:26,35:32","dtypep":"(BB)","keyword":"string","generic":true,"rangep": []}
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(ZB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
{"type":"MODULE","name":"@CONST-POOL@","addr":"(AC)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(AC)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(ZB)","varsp": [],"blocksp": [],"inlinesp": []}
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(BC)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(AC)","varsp": [],"blocksp": [],"inlinesp": []}
]}
]}
]}

2
test_regress/t/t_order_quad.v
View File

@ -7,11 +7,11 @@
// See issue #762
module t(a0, y);
input [3:0] a0;
// verilator lint_off UNOPTFLAT
output [44:0] y;
assign y[40] = 0;
assign y[30] = 0;
// verilator lint_off UNOPTFLAT
assign { y[44:41], y[39:31], y[29:0] } = { 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 };
endmodule

15
test_regress/t/t_timing_intra_assign_func.v
View File

@ -9,7 +9,7 @@ module t;
wire signed [3:0] iufunc;
// verilator lint_off WIDTH
assign #1 iufunc = int_func(ia);
assign #2 iufunc = int_func(ia);
// verilator lint_on WIDTH
function [31:0] int_func;
@ -17,9 +17,18 @@ module t;
int_func = in * 2;
endfunction
always @(iufunc) begin
if ($time > 0) begin
$display("time: %0t, iufunc: %0d", $time, iufunc);
if (iufunc != 4'd4) $stop;
if ($time != 3) $stop;
end
end
initial begin
#1
if (iufunc != 4'd2) $stop;
#1;
ia = 4'd2;
#10;
$write("*-* All Finished *-*\n");
$finish;
end

2
test_regress/t/t_unopt_combo_isolate.py
View File

@ -17,7 +17,7 @@ out_filename = test.obj_dir + "/V" + test.name + ".tree.json"
test.compile(verilator_flags2=["--no-json-edit-nums", "+define+ISOLATE", "--stats", "-fno-dfg"])
if test.vlt_all:
test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+3')
test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+4')
test.file_grep(
out_filename,
r'{"type":"VAR","name":"t.b",.*"loc":"\w,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"'

2
test_regress/t/t_unopt_combo_isolate_vlt.py
View File

@ -19,7 +19,7 @@ test.compile(verilator_flags2=[
])
if test.vlt_all:
test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+3')
test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+4')
test.file_grep(
out_filename,
r'{"type":"VAR","name":"t.b",.*"loc":"\w,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"'

10
test_regress/t/t_xml_first.out
View File

@ -49,10 +49,12 @@
<var loc="d,48,10,48,13" name="clk" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var loc="d,49,16,49,17" name="d" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var loc="d,50,22,50,23" name="q" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<contassign loc="d,53,13,53,14" dtype_id="1">
<varref loc="d,49,16,49,17" name="d" dtype_id="1"/>
<varref loc="d,53,13,53,14" name="q" dtype_id="1"/>
</contassign>
<always loc="d,53,13,53,14">
<contassign loc="d,53,13,53,14" dtype_id="1">
<varref loc="d,49,16,49,17" name="d" dtype_id="1"/>
<varref loc="d,53,13,53,14" name="q" dtype_id="1"/>
</contassign>
</always>
</module>
<module loc="d,31,8,31,12" name="mod1__W4" origName="mod1">
<var loc="d,32,15,32,20" name="WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">

100
test_regress/t/t_xml_flat.out
View File

@ -40,53 +40,71 @@
<varscope loc="d,13,10,13,13" name="clk" dtype_id="2"/>
<varscope loc="d,14,16,14,17" name="d" dtype_id="1"/>
<varscope loc="d,15,22,15,23" name="t.q" dtype_id="1"/>
<contassign loc="d,15,22,15,23" dtype_id="1">
<varref loc="d,15,22,15,23" name="q" dtype_id="1"/>
<varref loc="d,15,22,15,23" name="t.q" dtype_id="1"/>
</contassign>
<always loc="d,15,22,15,23">
<contassign loc="d,15,22,15,23" dtype_id="1">
<varref loc="d,15,22,15,23" name="q" dtype_id="1"/>
<varref loc="d,15,22,15,23" name="t.q" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,13,10,13,13" name="t.clk" dtype_id="2"/>
<contassign loc="d,13,10,13,13" dtype_id="2">
<varref loc="d,13,10,13,13" name="clk" dtype_id="2"/>
<varref loc="d,13,10,13,13" name="t.clk" dtype_id="2"/>
</contassign>
<always loc="d,13,10,13,13">
<contassign loc="d,13,10,13,13" dtype_id="2">
<varref loc="d,13,10,13,13" name="clk" dtype_id="2"/>
<varref loc="d,13,10,13,13" name="t.clk" dtype_id="2"/>
</contassign>
</always>
<varscope loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
<contassign loc="d,14,16,14,17" dtype_id="1">
<varref loc="d,14,16,14,17" name="d" dtype_id="1"/>
<varref loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
</contassign>
<always loc="d,14,16,14,17">
<contassign loc="d,14,16,14,17" dtype_id="1">
<varref loc="d,14,16,14,17" name="d" dtype_id="1"/>
<varref loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,17,22,17,29" name="t.between" dtype_id="1"/>
<varscope loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3"/>
<varscope loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
<contassign loc="d,34,24,34,27" dtype_id="2">
<varref loc="d,34,24,34,27" name="clk" dtype_id="2"/>
<varref loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
</contassign>
<always loc="d,34,24,34,27">
<contassign loc="d,34,24,34,27" dtype_id="2">
<varref loc="d,34,24,34,27" name="clk" dtype_id="2"/>
<varref loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
</contassign>
</always>
<varscope loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
<contassign loc="d,35,30,35,31" dtype_id="1">
<varref loc="d,35,30,35,31" name="d" dtype_id="1"/>
<varref loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
</contassign>
<always loc="d,35,30,35,31">
<contassign loc="d,35,30,35,31" dtype_id="1">
<varref loc="d,35,30,35,31" name="d" dtype_id="1"/>
<varref loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
<contassign loc="d,36,30,36,31" dtype_id="1">
<varref loc="d,36,30,36,31" name="t.between" dtype_id="1"/>
<varref loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
</contassign>
<always loc="d,36,30,36,31">
<contassign loc="d,36,30,36,31" dtype_id="1">
<varref loc="d,36,30,36,31" name="t.between" dtype_id="1"/>
<varref loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3"/>
<varscope loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
<contassign loc="d,48,10,48,13" dtype_id="2">
<varref loc="d,48,10,48,13" name="clk" dtype_id="2"/>
<varref loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
</contassign>
<always loc="d,48,10,48,13">
<contassign loc="d,48,10,48,13" dtype_id="2">
<varref loc="d,48,10,48,13" name="clk" dtype_id="2"/>
<varref loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
</contassign>
</always>
<varscope loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
<contassign loc="d,49,16,49,17" dtype_id="1">
<varref loc="d,49,16,49,17" name="t.between" dtype_id="1"/>
<varref loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
</contassign>
<always loc="d,49,16,49,17">
<contassign loc="d,49,16,49,17" dtype_id="1">
<varref loc="d,49,16,49,17" name="t.between" dtype_id="1"/>
<varref loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
<contassign loc="d,50,22,50,23" dtype_id="1">
<varref loc="d,50,22,50,23" name="q" dtype_id="1"/>
<varref loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
</contassign>
<always loc="d,50,22,50,23">
<contassign loc="d,50,22,50,23" dtype_id="1">
<varref loc="d,50,22,50,23" name="q" dtype_id="1"/>
<varref loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
</contassign>
</always>
<always loc="d,41,4,41,10">
<sentree loc="d,41,11,41,12">
<senitem loc="d,41,13,41,20" edgeType="POS">
@ -98,10 +116,12 @@
<varref loc="d,42,6,42,7" name="t.between" dtype_id="1"/>
</assigndly>
</always>
<contassign loc="d,53,13,53,14" dtype_id="1">
<varref loc="d,17,22,17,29" name="t.between" dtype_id="1"/>
<varref loc="d,53,13,53,14" name="q" dtype_id="1"/>
</contassign>
<always loc="d,53,13,53,14">
<contassign loc="d,53,13,53,14" dtype_id="1">
<varref loc="d,17,22,17,29" name="t.between" dtype_id="1"/>
<varref loc="d,53,13,53,14" name="q" dtype_id="1"/>
</contassign>
</always>
</scope>
</topscope>
</module>

20
test_regress/t/t_xml_flat_no_inline_mod.out
View File

@ -22,15 +22,19 @@
<scope loc="d,11,8,11,11" name="TOP">
<varscope loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varscope loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
<contassign loc="d,11,24,11,29" dtype_id="1">
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varref loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
</contassign>
<always loc="d,11,24,11,29">
<contassign loc="d,11,24,11,29" dtype_id="1">
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varref loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
<contassign loc="d,7,24,7,29" dtype_id="1">
<varref loc="d,7,24,7,29" name="i_clk" dtype_id="1"/>
<varref loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
</contassign>
<always loc="d,7,24,7,29">
<contassign loc="d,7,24,7,29" dtype_id="1">
<varref loc="d,7,24,7,29" name="i_clk" dtype_id="1"/>
<varref loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
</contassign>
</always>
</scope>
</topscope>
</module>

20
test_regress/t/t_xml_flat_pub_mod.out
View File

@ -22,15 +22,19 @@
<scope loc="d,11,8,11,11" name="TOP">
<varscope loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varscope loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
<contassign loc="d,11,24,11,29" dtype_id="1">
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varref loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
</contassign>
<always loc="d,11,24,11,29">
<contassign loc="d,11,24,11,29" dtype_id="1">
<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
<varref loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
<contassign loc="d,7,24,7,29" dtype_id="1">
<varref loc="d,7,24,7,29" name="i_clk" dtype_id="1"/>
<varref loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
</contassign>
<always loc="d,7,24,7,29">
<contassign loc="d,7,24,7,29" dtype_id="1">
<varref loc="d,7,24,7,29" name="i_clk" dtype_id="1"/>
<varref loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
</contassign>
</always>
</scope>
</topscope>
</module>

48
test_regress/t/t_xml_flat_vlvbound.out
View File

@ -30,25 +30,33 @@
<varscope loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
<varscope loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
<varscope loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1"/>
<contassign loc="d,9,25,9,28" dtype_id="1">
<varref loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
<varref loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1"/>
</contassign>
<always loc="d,9,25,9,28">
<contassign loc="d,9,25,9,28" dtype_id="1">
<varref loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
<varref loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1"/>
<contassign loc="d,10,25,10,28" dtype_id="1">
<varref loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
<varref loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1"/>
</contassign>
<always loc="d,10,25,10,28">
<contassign loc="d,10,25,10,28" dtype_id="1">
<varref loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
<varref loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1"/>
</contassign>
</always>
<varscope loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2"/>
<contassign loc="d,11,25,11,28" dtype_id="2">
<varref loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
<varref loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2"/>
</contassign>
<always loc="d,11,25,11,28">
<contassign loc="d,11,25,11,28" dtype_id="2">
<varref loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
<varref loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2"/>
</contassign>
</always>
<varscope loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2"/>
<contassign loc="d,12,25,12,28" dtype_id="2">
<varref loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
<varref loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2"/>
</contassign>
<always loc="d,12,25,12,28">
<contassign loc="d,12,25,12,28" dtype_id="2">
<varref loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
<varref loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2"/>
</contassign>
</always>
<varscope loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
<varscope loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
<varscope loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
@ -116,10 +124,10 @@
<varref loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
<varref loc="d,21,5,21,11" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
</assign>
<assign loc="d,24,14,24,15" dtype_id="2">
<contassign loc="d,24,14,24,15" dtype_id="2">
<varref loc="d,24,16,24,19" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
<varref loc="d,24,10,24,13" name="o_a" dtype_id="2"/>
</assign>
</contassign>
</always>
<always loc="d,25,14,25,15">
<comment loc="d,25,16,25,19" name="Function: foo"/>
@ -180,10 +188,10 @@
<varref loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
<varref loc="d,21,5,21,11" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
</assign>
<assign loc="d,25,14,25,15" dtype_id="2">
<contassign loc="d,25,14,25,15" dtype_id="2">
<varref loc="d,25,16,25,19" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
<varref loc="d,25,10,25,13" name="o_b" dtype_id="2"/>
</assign>
</contassign>
</always>
</scope>
</topscope>

10
test_regress/t/t_xml_tag.out
View File

@ -25,10 +25,12 @@
<var loc="d,29,8,29,12" name="itop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/>
<var loc="d,31,14,31,25" name="this_struct" tag="this_struct" dtype_id="4" vartype="" origName="this_struct"/>
<var loc="d,33,16,33,22" name="dotted" dtype_id="5" vartype="logic" origName="dotted"/>
<contassign loc="d,33,23,33,24" dtype_id="5">
<varxref loc="d,33,30,33,35" name="value" dtype_id="6" dotted="itop"/>
<varref loc="d,33,16,33,22" name="dotted" dtype_id="5"/>
</contassign>
<always loc="d,33,23,33,24">
<contassign loc="d,33,23,33,24" dtype_id="5">
<varxref loc="d,33,30,33,35" name="value" dtype_id="6" dotted="itop"/>
<varref loc="d,33,16,33,22" name="dotted" dtype_id="5"/>
</contassign>
</always>
<task loc="d,35,18,35,19" name="f">
<var loc="d,35,33,35,34" name="m" dtype_id="7" dir="input" vartype="string" origName="m"/>
<display loc="d,36,7,36,15" displaytype="$display">