diff --git a/test_regress/t/t_chg_first.py b/test_regress/t/t_always_chg_first.py similarity index 100% rename from test_regress/t/t_chg_first.py rename to test_regress/t/t_always_chg_first.py diff --git a/test_regress/t/t_chg_first.v b/test_regress/t/t_always_chg_first.v similarity index 100% rename from test_regress/t/t_chg_first.v rename to test_regress/t/t_always_chg_first.v diff --git a/test_regress/t/t_arraysel_wide.py b/test_regress/t/t_array_sel_wide.py similarity index 100% rename from test_regress/t/t_arraysel_wide.py rename to test_regress/t/t_array_sel_wide.py diff --git a/test_regress/t/t_arraysel_wide.v b/test_regress/t/t_array_sel_wide.v similarity index 100% rename from test_regress/t/t_arraysel_wide.v rename to test_regress/t/t_array_sel_wide.v diff --git a/test_regress/t/t_bench_mux4k.py b/test_regress/t/t_benchmark_mux4k.py similarity index 100% rename from test_regress/t/t_bench_mux4k.py rename to test_regress/t/t_benchmark_mux4k.py diff --git a/test_regress/t/t_bench_mux4k.v b/test_regress/t/t_benchmark_mux4k.v similarity index 100% rename from test_regress/t/t_bench_mux4k.v rename to test_regress/t/t_benchmark_mux4k.v diff --git a/test_regress/t/t_bench_mux4k_onecpu.py b/test_regress/t/t_benchmark_mux4k_onecpu.py similarity index 95% rename from test_regress/t/t_bench_mux4k_onecpu.py rename to test_regress/t/t_benchmark_mux4k_onecpu.py index d71cf4d42..cf7690988 100755 --- a/test_regress/t/t_bench_mux4k_onecpu.py +++ b/test_regress/t/t_benchmark_mux4k_onecpu.py @@ -10,7 +10,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.top_filename = "t/t_bench_mux4k.v" +test.top_filename = "t/t_benchmark_mux4k.v" test.compile(v_flags2=["--stats", test.wno_unopthreads_for_few_cores]) diff --git a/test_regress/t/t_benchmarksim.py b/test_regress/t/t_benchmark_sim.py similarity index 100% rename from test_regress/t/t_benchmarksim.py rename to test_regress/t/t_benchmark_sim.py diff --git a/test_regress/t/t_convert2string.py b/test_regress/t/t_clk_gated_1.py similarity index 100% rename from test_regress/t/t_convert2string.py rename to test_regress/t/t_clk_gated_1.py diff --git a/test_regress/t/t_gated_clk_1.v b/test_regress/t/t_clk_gated_1.v similarity index 100% rename from test_regress/t/t_gated_clk_1.v rename to test_regress/t/t_clk_gated_1.v diff --git a/test_regress/t/t_do_not_convert_to_comb.py b/test_regress/t/t_comb_do_not_convert_to.py similarity index 100% rename from test_regress/t/t_do_not_convert_to_comb.py rename to test_regress/t/t_comb_do_not_convert_to.py diff --git a/test_regress/t/t_do_not_convert_to_comb.v b/test_regress/t/t_comb_do_not_convert_to.v similarity index 100% rename from test_regress/t/t_do_not_convert_to_comb.v rename to test_regress/t/t_comb_do_not_convert_to.v diff --git a/test_regress/t/t_format_wide_decimal.out b/test_regress/t/t_display_format_wide_decimal.out similarity index 100% rename from test_regress/t/t_format_wide_decimal.out rename to test_regress/t/t_display_format_wide_decimal.out diff --git a/test_regress/t/t_format_wide_decimal.py b/test_regress/t/t_display_format_wide_decimal.py similarity index 89% rename from test_regress/t/t_format_wide_decimal.py rename to test_regress/t/t_display_format_wide_decimal.py index 957f7bb4c..ba4b18e85 100755 --- a/test_regress/t/t_format_wide_decimal.py +++ b/test_regress/t/t_display_format_wide_decimal.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["-Wall"]) +test.compile(verilator_flags2=["-Wall -Wno-DECLFILENAME"]) test.execute(expect_filename=test.golden_filename) diff --git a/test_regress/t/t_format_wide_decimal.v b/test_regress/t/t_display_format_wide_decimal.v similarity index 96% rename from test_regress/t/t_format_wide_decimal.v rename to test_regress/t/t_display_format_wide_decimal.v index b45b816e4..280571bbe 100644 --- a/test_regress/t/t_format_wide_decimal.v +++ b/test_regress/t/t_display_format_wide_decimal.v @@ -6,7 +6,7 @@ // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t_format_wide_decimal(/*AUTOARG*/ +module t(/*AUTOARG*/ // Inputs clk ); diff --git a/test_regress/t/t_continue_do_while_bad.out b/test_regress/t/t_do_while_continue_bad.out similarity index 83% rename from test_regress/t/t_continue_do_while_bad.out rename to test_regress/t/t_do_while_continue_bad.out index 797057234..db937c0fd 100644 --- a/test_regress/t/t_continue_do_while_bad.out +++ b/test_regress/t/t_do_while_continue_bad.out @@ -1,4 +1,4 @@ -%Warning-INFINITELOOP: t/t_continue_do_while_bad.v:14:7: Infinite loop (condition always true) +%Warning-INFINITELOOP: t/t_do_while_continue_bad.v:14:7: Infinite loop (condition always true) 14 | do begin | ^~ ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest diff --git a/test_regress/t/t_continue_do_while_bad.py b/test_regress/t/t_do_while_continue_bad.py similarity index 100% rename from test_regress/t/t_continue_do_while_bad.py rename to test_regress/t/t_do_while_continue_bad.py diff --git a/test_regress/t/t_continue_do_while_bad.v b/test_regress/t/t_do_while_continue_bad.v similarity index 100% rename from test_regress/t/t_continue_do_while_bad.v rename to test_regress/t/t_do_while_continue_bad.v diff --git a/test_regress/t/t_jumps_do_while.py b/test_regress/t/t_do_while_jumps.py similarity index 100% rename from test_regress/t/t_jumps_do_while.py rename to test_regress/t/t_do_while_jumps.py diff --git a/test_regress/t/t_jumps_do_while.v b/test_regress/t/t_do_while_jumps.v similarity index 100% rename from test_regress/t/t_jumps_do_while.v rename to test_regress/t/t_do_while_jumps.v diff --git a/test_regress/t/t_timeout.py b/test_regress/t/t_driver_timeout.py similarity index 100% rename from test_regress/t/t_timeout.py rename to test_regress/t/t_driver_timeout.py diff --git a/test_regress/t/t_dump_dfg.py b/test_regress/t/t_dump_dfg.py index 6c72c0fc0..6a8ee8087 100755 --- a/test_regress/t/t_dump_dfg.py +++ b/test_regress/t/t_dump_dfg.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('vlt') # For code coverage of graph dumping, so does not matter much what the input is -test.top_filename = "t/t_bench_mux4k.v" +test.top_filename = "t/t_benchmark_mux4k.v" test.compile(verilator_flags2=["--dump-dfg", "--dumpi-dfg 9"]) diff --git a/test_regress/t/t_output_groups.py b/test_regress/t/t_flag_output_groups.py similarity index 100% rename from test_regress/t/t_output_groups.py rename to test_regress/t/t_flag_output_groups.py diff --git a/test_regress/t/t_output_groups.v b/test_regress/t/t_flag_output_groups.v similarity index 100% rename from test_regress/t/t_output_groups.v rename to test_regress/t/t_flag_output_groups.v diff --git a/test_regress/t/t_duplicated_gen_blocks_bad.out b/test_regress/t/t_gen_duplicated_blocks_bad.out similarity index 70% rename from test_regress/t/t_duplicated_gen_blocks_bad.out rename to test_regress/t/t_gen_duplicated_blocks_bad.out index df9a128c0..f4c6fd043 100644 --- a/test_regress/t/t_duplicated_gen_blocks_bad.out +++ b/test_regress/t/t_gen_duplicated_blocks_bad.out @@ -1,16 +1,16 @@ -%Error: t/t_duplicated_gen_blocks_bad.v:11:12: Duplicate declaration of generate block: 'block' +%Error: t/t_gen_duplicated_blocks_bad.v:11:12: Duplicate declaration of generate block: 'block' : ... note: In instance 't' 11 | begin : block | ^~~~~ - t/t_duplicated_gen_blocks_bad.v:9:12: ... Location of original declaration + t/t_gen_duplicated_blocks_bad.v:9:12: ... Location of original declaration 9 | begin : block | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_duplicated_gen_blocks_bad.v:15:23: Duplicate declaration of generate block: 'block1' +%Error: t/t_gen_duplicated_blocks_bad.v:15:23: Duplicate declaration of generate block: 'block1' : ... note: In instance 't' 15 | if (X > 1) begin : block1 | ^~~~~~ - t/t_duplicated_gen_blocks_bad.v:13:23: ... Location of original declaration + t/t_gen_duplicated_blocks_bad.v:13:23: ... Location of original declaration 13 | if (X > 0) begin : block1 | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_duplicated_gen_blocks_bad.py b/test_regress/t/t_gen_duplicated_blocks_bad.py similarity index 100% rename from test_regress/t/t_duplicated_gen_blocks_bad.py rename to test_regress/t/t_gen_duplicated_blocks_bad.py diff --git a/test_regress/t/t_duplicated_gen_blocks_bad.v b/test_regress/t/t_gen_duplicated_blocks_bad.v similarity index 100% rename from test_regress/t/t_duplicated_gen_blocks_bad.v rename to test_regress/t/t_gen_duplicated_blocks_bad.v diff --git a/test_regress/t/t_bigmem_bad.out b/test_regress/t/t_mem_big_bad.out similarity index 55% rename from test_regress/t/t_bigmem_bad.out rename to test_regress/t/t_mem_big_bad.out index e502f93d5..c0dc80b82 100644 --- a/test_regress/t/t_bigmem_bad.out +++ b/test_regress/t/t_mem_big_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_bigmem_bad.v:14:19: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) - : ... note: In instance 't_bigmem' +%Error: t/t_mem_big_bad.v:14:19: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) + : ... note: In instance 't_bigmem' 14 | if (wen) mem[addr] <= data; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-WIDTHTRUNC: t/t_bigmem_bad.v:14:26: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'data' generates 256 bits. - : ... note: In instance 't_bigmem' +%Warning-WIDTHTRUNC: t/t_mem_big_bad.v:14:26: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'data' generates 256 bits. + : ... note: In instance 't_bigmem' 14 | if (wen) mem[addr] <= data; | ^~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest diff --git a/test_regress/t/t_bigmem_bad.py b/test_regress/t/t_mem_big_bad.py similarity index 100% rename from test_regress/t/t_bigmem_bad.py rename to test_regress/t/t_mem_big_bad.py diff --git a/test_regress/t/t_bigmem_bad.v b/test_regress/t/t_mem_big_bad.v similarity index 100% rename from test_regress/t/t_bigmem_bad.v rename to test_regress/t/t_mem_big_bad.v diff --git a/test_regress/t/t_dedupe_clk_gate.py b/test_regress/t/t_opt_dedupe_clk_gate.py similarity index 100% rename from test_regress/t/t_dedupe_clk_gate.py rename to test_regress/t/t_opt_dedupe_clk_gate.py diff --git a/test_regress/t/t_dedupe_clk_gate.v b/test_regress/t/t_opt_dedupe_clk_gate.v similarity index 100% rename from test_regress/t/t_dedupe_clk_gate.v rename to test_regress/t/t_opt_dedupe_clk_gate.v diff --git a/test_regress/t/t_dedupe_clk_gate_off.py b/test_regress/t/t_opt_dedupe_clk_gate_off.py similarity index 92% rename from test_regress/t/t_dedupe_clk_gate_off.py rename to test_regress/t/t_opt_dedupe_clk_gate_off.py index 534fe865b..e48d085c4 100755 --- a/test_regress/t/t_dedupe_clk_gate_off.py +++ b/test_regress/t/t_opt_dedupe_clk_gate_off.py @@ -10,7 +10,7 @@ import vltest_bootstrap test.scenarios('simulator_st') -test.top_filename = "t/t_dedupe_clk_gate.v" +test.top_filename = "t/t_opt_dedupe_clk_gate.v" test.compile(verilator_flags2=["--stats", "-fno-dedup"]) diff --git a/test_regress/t/t_dedupe_seq_logic.py b/test_regress/t/t_opt_dedupe_seq_logic.py similarity index 100% rename from test_regress/t/t_dedupe_seq_logic.py rename to test_regress/t/t_opt_dedupe_seq_logic.py diff --git a/test_regress/t/t_dedupe_seq_logic.v b/test_regress/t/t_opt_dedupe_seq_logic.v similarity index 100% rename from test_regress/t/t_dedupe_seq_logic.v rename to test_regress/t/t_opt_dedupe_seq_logic.v diff --git a/test_regress/t/t_gated_clk_1.py b/test_regress/t/t_opt_table_fsm.py similarity index 100% rename from test_regress/t/t_gated_clk_1.py rename to test_regress/t/t_opt_table_fsm.py diff --git a/test_regress/t/t_table_fsm.v b/test_regress/t/t_opt_table_fsm.v similarity index 100% rename from test_regress/t/t_table_fsm.v rename to test_regress/t/t_opt_table_fsm.v diff --git a/test_regress/t/t_bug6421.py b/test_regress/t/t_param_default_2.py similarity index 100% rename from test_regress/t/t_bug6421.py rename to test_regress/t/t_param_default_2.py diff --git a/test_regress/t/t_bug6421.v b/test_regress/t/t_param_default_2.v similarity index 100% rename from test_regress/t/t_bug6421.v rename to test_regress/t/t_param_default_2.v diff --git a/test_regress/t/t_cxx_equal_to.py b/test_regress/t/t_scope_cxx_equal_to.py similarity index 92% rename from test_regress/t/t_cxx_equal_to.py rename to test_regress/t/t_scope_cxx_equal_to.py index 0fb95e6fc..9df4d731c 100755 --- a/test_regress/t/t_cxx_equal_to.py +++ b/test_regress/t/t_scope_cxx_equal_to.py @@ -10,7 +10,6 @@ import vltest_bootstrap test.scenarios('simulator') -test.top_filename = "t/t_cxx_equal_to.v" test.compile(verilator_flags2=['--binary --trace-vcd']) diff --git a/test_regress/t/t_cxx_equal_to.v b/test_regress/t/t_scope_cxx_equal_to.v similarity index 100% rename from test_regress/t/t_cxx_equal_to.v rename to test_regress/t/t_scope_cxx_equal_to.v diff --git a/test_regress/t/t_nonsequential_udp.py b/test_regress/t/t_string_convert2.py similarity index 100% rename from test_regress/t/t_nonsequential_udp.py rename to test_regress/t/t_string_convert2.py diff --git a/test_regress/t/t_convert2string.v b/test_regress/t/t_string_convert2.v similarity index 100% rename from test_regress/t/t_convert2string.v rename to test_regress/t/t_string_convert2.v diff --git a/test_regress/t/t_trace_jumps_do_while_saif.py b/test_regress/t/t_trace_jumps_do_while_saif.py index 2cc4acfea..5b8126639 100755 --- a/test_regress/t/t_trace_jumps_do_while_saif.py +++ b/test_regress/t/t_trace_jumps_do_while_saif.py @@ -10,7 +10,7 @@ import vltest_bootstrap test.scenarios('vlt') -test.top_filename = "t/t_jumps_do_while.v" +test.top_filename = "t/t_do_while_jumps.v" test.compile(verilator_flags2=['--trace-saif']) diff --git a/test_regress/t/t_table_fsm.py b/test_regress/t/t_upd_nonsequential.py similarity index 100% rename from test_regress/t/t_table_fsm.py rename to test_regress/t/t_upd_nonsequential.py diff --git a/test_regress/t/t_nonsequential_udp.v b/test_regress/t/t_upd_nonsequential.v similarity index 100% rename from test_regress/t/t_nonsequential_udp.v rename to test_regress/t/t_upd_nonsequential.v