execute t_interface_typedef*
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@ -13,7 +13,6 @@ test.scenarios('simulator_st')
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test.compile(verilator_flags2=['--binary'])
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test.compile(verilator_flags2=['--binary'])
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if not test.vlt_all:
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test.execute()
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test.execute()
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test.passes()
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test.passes()
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@ -6,7 +6,7 @@
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// verilog_format: off
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// verilog_format: off
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`define stop $stop
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`define stop $stop
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`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: (%m) %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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// verilog_format: on
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interface ifc #(
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interface ifc #(
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@ -46,15 +46,15 @@ module sub #(
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input logic clk,
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input logic clk,
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ifc ifc_if
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ifc ifc_if
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);
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);
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typedef ifc_if.struct_t struct_t;
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typedef ifc_if.struct_t my_struct_t;
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wire [EXP_WIDTH-1:0] expval = '1;
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wire [EXP_WIDTH-1:0] expval = '1;
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initial begin
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initial begin
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struct_t substruct;
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my_struct_t substruct;
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#10;
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#10;
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substruct.data = '1;
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substruct.data = '1;
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`checkh($bits(struct_t), EXP_WIDTH);
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`checkh($bits(my_struct_t), EXP_WIDTH);
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`checkh(substruct.data, expval);
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`checkh(substruct.data, expval);
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end
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end
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@ -13,7 +13,6 @@ test.scenarios('simulator_st')
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test.compile(verilator_flags2=['--binary'])
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test.compile(verilator_flags2=['--binary'])
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if not test.vlt_all:
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test.execute()
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test.execute()
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test.passes()
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test.passes()
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