From e8fcbb0fa08f25927e9db86c04e661a375715cde Mon Sep 17 00:00:00 2001
From: Todd Strader <tstrader@hudson-trading.com>
Date: Fri, 30 Jan 2026 09:38:52 -0500
Subject: [PATCH] execute t_interface_typedef*

---
 test_regress/t/t_interface_typedef.py  | 3 +--
 test_regress/t/t_interface_typedef.v   | 8 ++++----
 test_regress/t/t_interface_typedef2.py | 3 +--
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/test_regress/t/t_interface_typedef.py b/test_regress/t/t_interface_typedef.py
index a87f14d38..096e10e28 100755
--- a/test_regress/t/t_interface_typedef.py
+++ b/test_regress/t/t_interface_typedef.py
@@ -13,7 +13,6 @@ test.scenarios('simulator_st')
 
 test.compile(verilator_flags2=['--binary'])
 
-if not test.vlt_all:
-    test.execute()
+test.execute()
 
 test.passes()
diff --git a/test_regress/t/t_interface_typedef.v b/test_regress/t/t_interface_typedef.v
index abb21d448..35e3fc371 100644
--- a/test_regress/t/t_interface_typedef.v
+++ b/test_regress/t/t_interface_typedef.v
@@ -6,7 +6,7 @@
 
 // verilog_format: off
 `define stop $stop
-`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: (%m) %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
 // verilog_format: on
 
 interface ifc #(
@@ -46,15 +46,15 @@ module sub #(
     input logic clk,
     ifc ifc_if
 );
-  typedef ifc_if.struct_t struct_t;
+  typedef ifc_if.struct_t my_struct_t;
 
   wire [EXP_WIDTH-1:0] expval = '1;
 
   initial begin
-    struct_t substruct;
+    my_struct_t substruct;
     #10;
     substruct.data = '1;
-    `checkh($bits(struct_t), EXP_WIDTH);
+    `checkh($bits(my_struct_t), EXP_WIDTH);
     `checkh(substruct.data, expval);
   end
 
diff --git a/test_regress/t/t_interface_typedef2.py b/test_regress/t/t_interface_typedef2.py
index a87f14d38..096e10e28 100755
--- a/test_regress/t/t_interface_typedef2.py
+++ b/test_regress/t/t_interface_typedef2.py
@@ -13,7 +13,6 @@ test.scenarios('simulator_st')
 
 test.compile(verilator_flags2=['--binary'])
 
-if not test.vlt_all:
-    test.execute()
+test.execute()
 
 test.passes()