diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS
index a3fca586c..f43f79424 100644
--- a/docs/CONTRIBUTORS
+++ b/docs/CONTRIBUTORS
@@ -281,5 +281,6 @@ dependabot[bot]
 february cozzocrea
 sumpster
 em2machine
+emmettifelts
 Àlex Torregrosa
 Ícaro Lima
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 9830d6737..5299a4e19 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -4868,6 +4868,10 @@ class WidthVisitor final : public VNVisitor {
             nodep->v3warn(E_UNSUPPORTED, "Unsupported/Illegal: Assignment pattern"
                                          " member not underneath a supported construct: "
                                              << nodep->backp()->prettyTypeName());
+
+            if (nodep->backp() && (VN_IS(nodep->backp(), Eq) || VN_IS(nodep->backp(), Neq))) return;
+            nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}});
+            VL_DO_DANGLING(pushDeletep(nodep), nodep);
             return;
         }
         {
diff --git a/test_regress/t/t_pattern_unsup_xor.out b/test_regress/t/t_pattern_unsup_xor.out
new file mode 100644
index 000000000..e9ed07969
--- /dev/null
+++ b/test_regress/t/t_pattern_unsup_xor.out
@@ -0,0 +1,6 @@
+%Error-UNSUPPORTED: t/t_pattern_unsup_xor.v:13:25: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: XOR
+                                                 : ... note: In instance 't'
+   13 |   status_t status_reg = '{bit_field: 1'b0} ^ 1'b0;
+      |                         ^~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to
diff --git a/test_regress/t/t_pattern_unsup_xor.py b/test_regress/t/t_pattern_unsup_xor.py
new file mode 100644
index 000000000..31228c9a7
--- /dev/null
+++ b/test_regress/t/t_pattern_unsup_xor.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_pattern_unsup_xor.v b/test_regress/t/t_pattern_unsup_xor.v
new file mode 100644
index 000000000..87f4f5acf
--- /dev/null
+++ b/test_regress/t/t_pattern_unsup_xor.v
@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// Test for issue where assignment pattern with XOR caused segfault
+module t;
+  typedef struct {
+    logic bit_field;
+  } status_t;
+
+  status_t status_reg = '{bit_field: 1'b0} ^ 1'b0;
+endmodule