[#72179] add t_timing_trace_saif test

test_regress/t/t_timing_trace_saif.out

@@ -0,0 +1,19 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "foo")
+(PROGRAM_NAME "Verilator")
+(VERSION "5.032")
+(DIVIDER .)
+(TIMESCALE 1ps)
+(DURATION 100)
+(INSTANCE foo (NET
+(c (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+(b (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+(clk (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 20))
+(rst (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+(CLK_HALF_PERIOD[0] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+(CLK_HALF_PERIOD[2] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+(CLK_PERIOD[1] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+(CLK_PERIOD[3] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+)))

test_regress/t/t_timing_trace_saif.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_timing_trace.v"
+
+test.compile(verilator_flags2=["--exe --main --timing --trace-saif -Wno-MINTYPMAXDLY"])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()