aggregated iface tests into single test
This commit is contained in:
em2machine
parent
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commit
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0
test_regress/t/t_multidriven_iface0.py → test_regress/t/t_multidriven_iface.py
Executable file → Normal file
0
test_regress/t/t_multidriven_iface0.py → test_regress/t/t_multidriven_iface.py
Executable file → Normal file
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@ -0,0 +1,235 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// Consolidated interface-based multidriven tests
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// (formerly t_multidriven_iface{0,1,2,3,4,5,6}.v)
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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//----------------------------------------------------------------------
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// iface0: direct assignment to interface signal + interface task assign in same process
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interface my_if0;
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logic l0;
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task set_l0_1(); l0 = 1'b1; endtask
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task set_l0_0(); l0 = 1'b0; endtask
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endinterface
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module iface0 #()(
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input logic sel,
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output logic val
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);
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my_if0 if0();
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always_comb begin
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if0.l0 = 1'b0;
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if (sel) begin
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if0.set_l0_1();
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end
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end
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assign val = if0.l0;
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endmodule
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//----------------------------------------------------------------------
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// iface1: interface task chain - nested calls write interface signal in same always_comb
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interface my_if1;
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logic l0;
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task set_l0_1_inner(); l0 = 1'b1; endtask
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task set_l0_1_outer(); set_l0_1_inner(); endtask
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endinterface
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module iface1 #()(
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input logic sel,
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output logic val
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);
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my_if1 if0();
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always_comb begin
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if0.l0 = 1'b0;
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if (sel) begin
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if0.set_l0_1_outer();
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end
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end
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assign val = if0.l0;
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endmodule
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//----------------------------------------------------------------------
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// iface2: interface passed through module port - direct assign + task call in same always_comb
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interface my_if2;
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logic l0;
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task set_l0_1(); l0 = 1'b1; endtask
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task set_l0_0(); l0 = 1'b0; endtask
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endinterface
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module iface2 #()(
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input logic sel,
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output logic val,
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my_if2 ifp
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);
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always_comb begin
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ifp.l0 = 1'b0;
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if (sel) begin
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ifp.set_l0_1();
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end
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end
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assign val = ifp.l0;
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endmodule
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//----------------------------------------------------------------------
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// iface3: interface modport + task import - write interface signal in same always_comb
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interface my_if3;
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logic l0;
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task set_l0_1(); l0 = 1'b1; endtask
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modport mp (
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output l0,
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import set_l0_1
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);
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endinterface
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module iface3 #()(
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input logic sel,
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output logic val,
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my_if3.mp ifp
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);
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always_comb begin
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ifp.l0 = 1'b0;
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if (sel) begin
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ifp.set_l0_1();
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end
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end
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assign val = ifp.l0;
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endmodule
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//----------------------------------------------------------------------
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// iface4: interface task writes through output formal - actual is interface member
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interface my_if4;
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logic l0;
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task automatic set_any(output logic q);
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q = 1'b1;
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endtask
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endinterface
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module iface4 #()(
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input logic sel,
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output logic val
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);
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my_if4 if0();
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always_comb begin
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if0.l0 = 1'b0;
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if (sel) begin
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if0.set_any(if0.l0);
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end
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end
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assign val = if0.l0;
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endmodule
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//----------------------------------------------------------------------
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// iface5: nested interface test - direct assignment + nested interface task call in same always_comb
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interface leaf_if5;
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logic l0;
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task set1(); l0 = 1'b1; endtask
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endinterface
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interface top_if5;
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leaf_if5 sub();
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endinterface
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module iface5 #()(
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input logic sel,
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output logic val
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);
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top_if5 if0();
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always_comb begin
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if0.sub.l0 = 1'b0;
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if (sel) begin
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if0.sub.set1();
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end
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end
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assign val = if0.sub.l0;
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endmodule
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//----------------------------------------------------------------------
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// iface6: nested interface aggregator - two nested interfaces, only one driven
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interface chan_if6;
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logic b0;
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task set1(); b0 = 1'b1; endtask
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endinterface
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interface agg_if6;
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chan_if6 tlb();
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chan_if6 ic();
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endinterface
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module iface6 #()(
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input logic sel,
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output logic val
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);
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agg_if6 a();
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always_comb begin
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a.tlb.b0 = 1'b0;
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if (sel) a.tlb.set1();
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end
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assign val = a.tlb.b0;
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endmodule
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//----------------------------------------------------------------------
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// Shared TB
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module m_tb#()();
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logic sel;
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logic val0, val1, val2, val3, val4, val5, val6;
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my_if2 if2();
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my_if3 if3();
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iface0 u0(.sel(sel), .val(val0));
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iface1 u1(.sel(sel), .val(val1));
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iface2 u2(.sel(sel), .val(val2), .ifp(if2));
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iface3 u3(.sel(sel), .val(val3), .ifp(if3));
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iface4 u4(.sel(sel), .val(val4));
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iface5 u5(.sel(sel), .val(val5));
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iface6 u6(.sel(sel), .val(val6));
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task automatic check_all(input logic exp);
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`checkd(val0, exp);
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`checkd(val1, exp);
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`checkd(val2, exp);
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`checkd(val3, exp);
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`checkd(val4, exp);
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`checkd(val5, exp);
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`checkd(val6, exp);
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endtask
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initial begin
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#1;
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sel = 'b0;
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#1;
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check_all(1'b0);
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sel = 'b1;
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#1;
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check_all(1'b1);
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sel = 'b0;
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#1;
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check_all(1'b0);
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end
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initial begin
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#5;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -1,68 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// multidriven interface test - direct assignment to interface signal and task assign in same process
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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interface my_if;
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logic l0;
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task set_l0_1(); l0 = 1'b1; endtask
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task set_l0_0(); l0 = 1'b0; endtask
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endinterface
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module mod #()(
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input logic sel
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,output logic val
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);
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my_if if0();
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always_comb begin
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if0.l0 = 1'b0;
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if(sel) begin
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if0.set_l0_1();
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end
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end
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assign val = if0.l0;
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endmodule
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module m_tb#()();
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logic sel, val;
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mod m(
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.sel(sel)
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,.val(val)
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);
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initial begin
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#1;
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sel = 'b0;
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`checkd(val, 1'b0);
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#1;
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sel = 'b1;
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`checkd(val, 1'b1);
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#1;
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sel = 'b0;
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`checkd(val, 1'b0);
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#1;
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end
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initial begin
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#5;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -1,18 +0,0 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--binary"])
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test.execute()
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test.passes()
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@ -1,68 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// interface task chain - nested task calls write interface signal in same always_comb
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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interface my_if;
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logic l0;
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task set_l0_1_inner(); l0 = 1'b1; endtask
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task set_l0_1_outer(); set_l0_1_inner(); endtask
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endinterface
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module mod #()(
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input logic sel
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,output logic val
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);
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my_if if0();
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always_comb begin
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if0.l0 = 1'b0;
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if (sel) begin
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if0.set_l0_1_outer();
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end
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end
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assign val = if0.l0;
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endmodule
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module m_tb#()();
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logic sel, val;
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mod m(
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.sel(sel)
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,.val(val)
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);
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initial begin
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#1;
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sel = 'b0;
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`checkd(val, 1'b0);
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#1;
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sel = 'b1;
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`checkd(val, 1'b1);
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#1;
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sel = 'b0;
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`checkd(val, 1'b0);
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#1;
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end
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initial begin
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#5;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -1,18 +0,0 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--binary"])
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test.execute()
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test.passes()
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@ -1,69 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
|
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//
|
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// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// interface passed through module port - direct assign + task call in same always_comb
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|
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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|
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interface my_if;
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logic l0;
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task set_l0_1(); l0 = 1'b1; endtask
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task set_l0_0(); l0 = 1'b0; endtask
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endinterface
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module mod #()(
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input logic sel
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,output logic val
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,my_if ifp
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);
|
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|
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always_comb begin
|
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ifp.l0 = 1'b0;
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|
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if (sel) begin
|
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ifp.set_l0_1();
|
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end
|
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end
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|
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assign val = ifp.l0;
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|
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endmodule
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module m_tb#()();
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|
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logic sel, val;
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my_if if0();
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mod m(
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.sel(sel)
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,.val(val)
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,.ifp(if0)
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);
|
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|
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initial begin
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#1;
|
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sel = 'b0;
|
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`checkd(val, 1'b0);
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#1;
|
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sel = 'b1;
|
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`checkd(val, 1'b1);
|
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#1;
|
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sel = 'b0;
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`checkd(val, 1'b0);
|
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#1;
|
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end
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|
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initial begin
|
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#5;
|
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$write("*-* All Finished *-*\n");
|
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$finish;
|
||||
end
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|
||||
endmodule
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|
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@ -1,18 +0,0 @@
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#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
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|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// interface modport + task import - write interface signal in same always_comb
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
interface my_if;
|
||||
logic l0;
|
||||
|
||||
task set_l0_1(); l0 = 1'b1; endtask
|
||||
|
||||
modport mp (
|
||||
output l0,
|
||||
import set_l0_1
|
||||
);
|
||||
endinterface
|
||||
|
||||
module mod #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
,my_if.mp ifp
|
||||
);
|
||||
|
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always_comb begin
|
||||
ifp.l0 = 1'b0;
|
||||
|
||||
if (sel) begin
|
||||
ifp.set_l0_1();
|
||||
end
|
||||
end
|
||||
|
||||
assign val = ifp.l0;
|
||||
|
||||
endmodule
|
||||
|
||||
module m_tb#()();
|
||||
|
||||
logic sel, val;
|
||||
my_if if0();
|
||||
|
||||
mod m(
|
||||
.sel(sel)
|
||||
,.val(val)
|
||||
,.ifp(if0)
|
||||
);
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
sel = 'b0;
|
||||
`checkd(val, 1'b0);
|
||||
#1;
|
||||
sel = 'b1;
|
||||
`checkd(val, 1'b1);
|
||||
#1;
|
||||
sel = 'b0;
|
||||
`checkd(val, 1'b0);
|
||||
#1;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// interface task writes through output formal - actual is interface member
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
interface my_if;
|
||||
logic l0;
|
||||
|
||||
task automatic set_any(output logic q);
|
||||
q = 1'b1;
|
||||
endtask
|
||||
endinterface
|
||||
|
||||
module mod #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
my_if if0();
|
||||
|
||||
always_comb begin
|
||||
if0.l0 = 1'b0;
|
||||
|
||||
if (sel) begin
|
||||
if0.set_any(if0.l0);
|
||||
end
|
||||
end
|
||||
|
||||
assign val = if0.l0;
|
||||
|
||||
endmodule
|
||||
|
||||
module m_tb#()();
|
||||
|
||||
logic sel, val;
|
||||
|
||||
mod m(
|
||||
.sel(sel)
|
||||
,.val(val)
|
||||
);
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
sel = 'b0;
|
||||
`checkd(val, 1'b0);
|
||||
#1;
|
||||
sel = 'b1;
|
||||
`checkd(val, 1'b1);
|
||||
#1;
|
||||
sel = 'b0;
|
||||
`checkd(val, 1'b0);
|
||||
#1;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// nested interface test - direct assignment + nested interface task call in same always_comb
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
interface leaf_if;
|
||||
logic l0;
|
||||
task set1(); l0 = 1'b1; endtask
|
||||
endinterface
|
||||
|
||||
interface top_if;
|
||||
leaf_if sub();
|
||||
endinterface
|
||||
|
||||
module mod #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
top_if if0();
|
||||
|
||||
always_comb begin
|
||||
if0.sub.l0 = 1'b0;
|
||||
if (sel) begin
|
||||
if0.sub.set1();
|
||||
end
|
||||
end
|
||||
|
||||
assign val = if0.sub.l0;
|
||||
|
||||
endmodule
|
||||
|
||||
module m_tb#()();
|
||||
|
||||
logic sel, val;
|
||||
|
||||
mod m(
|
||||
.sel(sel)
|
||||
,.val(val)
|
||||
);
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
sel = 'b0;
|
||||
`checkd(val, 1'b0);
|
||||
#1;
|
||||
sel = 'b1;
|
||||
`checkd(val, 1'b1);
|
||||
#1;
|
||||
sel = 'b0;
|
||||
`checkd(val, 1'b0);
|
||||
#1;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// nested interface aggregator - two nested interfaces, only one driven
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
interface chan_if;
|
||||
logic b0;
|
||||
task set1(); b0 = 1'b1; endtask
|
||||
endinterface
|
||||
|
||||
interface agg_if;
|
||||
chan_if tlb();
|
||||
chan_if ic();
|
||||
endinterface
|
||||
|
||||
module mod #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
agg_if a();
|
||||
|
||||
always_comb begin
|
||||
a.tlb.b0 = 1'b0;
|
||||
if (sel) a.tlb.set1();
|
||||
end
|
||||
|
||||
assign val = a.tlb.b0;
|
||||
|
||||
endmodule
|
||||
|
||||
module m_tb#()();
|
||||
|
||||
logic sel, val;
|
||||
|
||||
mod m(
|
||||
.sel(sel)
|
||||
,.val(val)
|
||||
);
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
sel = 'b0;
|
||||
`checkd(val, 1'b0);
|
||||
#1;
|
||||
sel = 'b1;
|
||||
`checkd(val, 1'b1);
|
||||
#1;
|
||||
sel = 'b0;
|
||||
`checkd(val, 1'b0);
|
||||
#1;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue