coalesced class tests into a single test
This commit is contained in:
em2machine
parent
d2146f0e56
commit
8e55fa1f05
0
test_regress/t/t_multidriven_class0.py → test_regress/t/t_multidriven_class.py
Executable file → Normal file
0
test_regress/t/t_multidriven_class0.py → test_regress/t/t_multidriven_class.py
Executable file → Normal file
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@ -0,0 +1,284 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// Consolidated class-based task/function multidriven tests
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// (formerly t_multidriven_class{0,1,2,3,4,f0,f1}.v)
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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//----------------------------------------------------------------------
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// class0: class task writes through ref argument (direct assignment + class task in same always_comb)
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class C0;
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task automatic set1(ref logic q);
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q = 1'b1;
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endtask
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task automatic set0(ref logic q);
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q = 1'b0;
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endtask
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endclass
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module class0 #()(
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input logic sel
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,output logic val
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);
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logic l0;
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C0 c;
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initial c = new;
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always_comb begin
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l0 = 1'b0;
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if (sel) begin
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c.set1(l0);
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end
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end
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assign val = l0;
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endmodule
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//----------------------------------------------------------------------
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// class1: class task chain - nested method calls write through ref in same always_comb
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class C1;
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task automatic inner(inout logic q);
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q = 1'b1;
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endtask
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task automatic outer(inout logic q);
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inner(q);
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endtask
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endclass
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module class1 #()(
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input logic sel
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,output logic val
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);
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logic l0;
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C1 c;
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initial c = new;
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always_comb begin
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l0 = 1'b0;
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if (sel) begin
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c.outer(l0);
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end
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end
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assign val = l0;
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endmodule
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//----------------------------------------------------------------------
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// class2: class handle passed through module port - class method writes through ref
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class C2;
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task automatic set1(ref logic q);
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q = 1'b1;
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endtask
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endclass
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module class2 #()(
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input logic sel
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,output logic val
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,C2 c
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);
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logic l0;
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always_comb begin
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l0 = 1'b0;
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if (sel) begin
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c.set1(l0);
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end
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end
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assign val = l0;
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endmodule
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//----------------------------------------------------------------------
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// class3: static class task - call via class scope, writes through ref in same always_comb
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class C3;
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static task automatic set1(ref logic q);
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q = 1'b1;
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endtask
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endclass
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module class3 #()(
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input logic sel
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,output logic val
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);
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logic l0;
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always_comb begin
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l0 = 1'b0;
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if (sel) begin
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C3::set1(l0);
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end
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end
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assign val = l0;
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endmodule
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//----------------------------------------------------------------------
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// class4: class composition - one class calls another task, ultimately writes through ref
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class C4Inner;
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task automatic set1(ref logic q);
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q = 1'b1;
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endtask
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endclass
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class C4Outer;
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C4Inner inner;
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function new();
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inner = new;
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endfunction
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task automatic set1(ref logic q);
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inner.set1(q);
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endtask
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endclass
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module class4 #()(
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input logic sel
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,output logic val
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);
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logic l0;
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C4Outer c;
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initial c = new;
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always_comb begin
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l0 = 1'b0;
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if (sel) begin
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c.set1(l0);
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end
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end
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assign val = l0;
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endmodule
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//----------------------------------------------------------------------
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// classf0: class function returns value - always_comb writes var directly + via class function call
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class Cf0;
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function automatic logic ret1();
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return 1'b1;
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endfunction
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endclass
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module classf0 #()(
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input logic sel
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,output logic val
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);
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logic l0;
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Cf0 c;
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initial c = new;
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always_comb begin
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l0 = 1'b0;
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if (sel) begin
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l0 = c.ret1();
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end
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end
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assign val = l0;
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endmodule
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//----------------------------------------------------------------------
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// classf1: static class function returns value - always_comb uses class scope call
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class Cf1;
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static function automatic logic ret1();
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return 1'b1;
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endfunction
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endclass
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module classf1 #()(
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input logic sel
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,output logic val
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);
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logic l0;
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always_comb begin
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l0 = 1'b0;
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if (sel) begin
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l0 = Cf1::ret1();
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end
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end
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assign val = l0;
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endmodule
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//----------------------------------------------------------------------
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// Shared TB
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module m_tb#()();
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logic sel;
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logic val0, val1, val2, val3, val4, valf0, valf1;
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C2 c2;
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initial c2 = new;
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class0 u0(.sel(sel), .val(val0));
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class1 u1(.sel(sel), .val(val1));
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class2 u2(.sel(sel), .val(val2), .c(c2));
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class3 u3(.sel(sel), .val(val3));
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class4 u4(.sel(sel), .val(val4));
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classf0 uf0(.sel(sel), .val(valf0));
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classf1 uf1(.sel(sel), .val(valf1));
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task automatic check_all(input logic exp);
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`checkd(val0, exp);
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`checkd(val1, exp);
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`checkd(val2, exp);
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`checkd(val3, exp);
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`checkd(val4, exp);
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`checkd(valf0, exp);
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`checkd(valf1, exp);
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endtask
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initial begin
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#1;
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sel = 'b0;
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#1;
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check_all(1'b0);
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sel = 'b1;
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#1;
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check_all(1'b1);
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sel = 'b0;
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#1;
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check_all(1'b0);
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end
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initial begin
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#5;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -1,72 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// class task writes through ref argument (direct assignment + class task in same always_comb)
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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class C;
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task automatic set1(ref logic q);
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q = 1'b1;
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endtask
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task automatic set0(ref logic q);
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q = 1'b0;
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endtask
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endclass
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module mod #()(
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input logic sel
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,output logic val
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);
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logic l0;
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C c;
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initial c = new;
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always_comb begin
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l0 = 1'b0;
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if (sel) begin
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c.set1(l0);
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end
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end
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assign val = l0;
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endmodule
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module m_tb#()();
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logic sel, val;
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mod m(
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.sel(sel)
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,.val(val)
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);
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initial begin
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#1;
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sel = 'b0;
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#1;
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`checkd(val, 1'b0);
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sel = 'b1;
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#1;
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`checkd(val, 1'b1);
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sel = 'b0;
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#1;
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`checkd(val, 1'b0);
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end
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initial begin
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#5;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -1,18 +0,0 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--binary"])
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test.execute()
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test.passes()
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@ -1,72 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
|
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// SPDX-License-Identifier: CC0-1.0
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// class task chain - nested method calls write through ref in same always_comb
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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class C;
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task automatic inner(inout logic q);
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q = 1'b1;
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endtask
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task automatic outer(inout logic q);
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inner(q);
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endtask
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endclass
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module mod #()(
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input logic sel
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,output logic val
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);
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logic l0;
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C c;
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initial c = new;
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always_comb begin
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l0 = 1'b0;
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if (sel) begin
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c.outer(l0);
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end
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end
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assign val = l0;
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endmodule
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module m_tb#()();
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logic sel, val;
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mod m(
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.sel(sel)
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,.val(val)
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);
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initial begin
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#1;
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sel = 'b0;
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#1;
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`checkd(val, 1'b0);
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sel = 'b1;
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#1;
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`checkd(val, 1'b1);
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sel = 'b0;
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#1;
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`checkd(val, 1'b0);
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end
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initial begin
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#5;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -1,18 +0,0 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
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# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
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|
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import vltest_bootstrap
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|
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test.scenarios('simulator')
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|
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test.compile(verilator_flags2=["--binary"])
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test.execute()
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test.passes()
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|
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@ -1,71 +0,0 @@
|
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// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// class handle passed through module port - class method writes through ref
|
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|
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// verilog_format: off
|
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`define stop $stop
|
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
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// verilog_format: on
|
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|
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class C;
|
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task automatic set1(ref logic q);
|
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q = 1'b1;
|
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endtask
|
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endclass
|
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|
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module mod #()(
|
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input logic sel
|
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,output logic val
|
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,C c
|
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);
|
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|
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logic l0;
|
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|
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always_comb begin
|
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l0 = 1'b0;
|
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if (sel) begin
|
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c.set1(l0);
|
||||
end
|
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end
|
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|
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assign val = l0;
|
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|
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endmodule
|
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|
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module m_tb#()();
|
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|
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logic sel, val;
|
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C c;
|
||||
|
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initial c = new;
|
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|
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mod m(
|
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.sel(sel)
|
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,.val(val)
|
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,.c(c)
|
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);
|
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|
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initial begin
|
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#1;
|
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sel = 'b0;
|
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#1;
|
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`checkd(val, 1'b0);
|
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sel = 'b1;
|
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#1;
|
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`checkd(val, 1'b1);
|
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sel = 'b0;
|
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#1;
|
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`checkd(val, 1'b0);
|
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end
|
||||
|
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initial begin
|
||||
#5;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
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|
||||
endmodule
|
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|
|
@ -1,18 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// static class task - call via class scope, writes through ref in same always_comb
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
class C;
|
||||
static task automatic set1(ref logic q);
|
||||
q = 1'b1;
|
||||
endtask
|
||||
endclass
|
||||
|
||||
module mod #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
logic l0;
|
||||
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) begin
|
||||
C::set1(l0);
|
||||
end
|
||||
end
|
||||
|
||||
assign val = l0;
|
||||
|
||||
endmodule
|
||||
|
||||
module m_tb#()();
|
||||
|
||||
logic sel, val;
|
||||
|
||||
mod m(
|
||||
.sel(sel)
|
||||
,.val(val)
|
||||
);
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
sel = 'b0;
|
||||
#1;
|
||||
`checkd(val, 1'b0);
|
||||
sel = 'b1;
|
||||
#1;
|
||||
`checkd(val, 1'b1);
|
||||
sel = 'b0;
|
||||
#1;
|
||||
`checkd(val, 1'b0);
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -1,79 +0,0 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// class composition - one class calls another task, ultimately writes through ref
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
class CInner;
|
||||
task automatic set1(ref logic q);
|
||||
q = 1'b1;
|
||||
endtask
|
||||
endclass
|
||||
|
||||
class COuter;
|
||||
CInner inner;
|
||||
function new();
|
||||
inner = new;
|
||||
endfunction
|
||||
task automatic set1(ref logic q);
|
||||
inner.set1(q);
|
||||
endtask
|
||||
endclass
|
||||
|
||||
module mod #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
logic l0;
|
||||
COuter c;
|
||||
|
||||
initial c = new;
|
||||
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) begin
|
||||
c.set1(l0);
|
||||
end
|
||||
end
|
||||
|
||||
assign val = l0;
|
||||
|
||||
endmodule
|
||||
|
||||
module m_tb#()();
|
||||
|
||||
logic sel, val;
|
||||
|
||||
mod m(
|
||||
.sel(sel)
|
||||
,.val(val)
|
||||
);
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
sel = 'b0;
|
||||
#1;
|
||||
`checkd(val, 1'b0);
|
||||
sel = 'b1;
|
||||
#1;
|
||||
`checkd(val, 1'b1);
|
||||
sel = 'b0;
|
||||
#1;
|
||||
`checkd(val, 1'b0);
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -1,69 +0,0 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// class function returns value - always_comb writes var directly + via class function call
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
class C;
|
||||
function automatic logic ret1();
|
||||
return 1'b1;
|
||||
endfunction
|
||||
endclass
|
||||
|
||||
module mod #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
logic l0;
|
||||
C c;
|
||||
|
||||
initial c = new;
|
||||
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) begin
|
||||
l0 = c.ret1();
|
||||
end
|
||||
end
|
||||
|
||||
assign val = l0;
|
||||
|
||||
endmodule
|
||||
|
||||
module m_tb#()();
|
||||
|
||||
logic sel, val;
|
||||
|
||||
mod m(
|
||||
.sel(sel)
|
||||
,.val(val)
|
||||
);
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
sel = 'b0;
|
||||
#1;
|
||||
`checkd(val, 1'b0);
|
||||
sel = 'b1;
|
||||
#1;
|
||||
`checkd(val, 1'b1);
|
||||
sel = 'b0;
|
||||
#1;
|
||||
`checkd(val, 1'b0);
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2025 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('simulator')
|
||||
|
||||
test.compile(verilator_flags2=["--binary"])
|
||||
|
||||
test.execute()
|
||||
|
||||
test.passes()
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
// static class function returns value - always_comb uses class scope call
|
||||
|
||||
// verilog_format: off
|
||||
`define stop $stop
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
|
||||
// verilog_format: on
|
||||
|
||||
class C;
|
||||
static function automatic logic ret1();
|
||||
return 1'b1;
|
||||
endfunction
|
||||
endclass
|
||||
|
||||
module mod #()(
|
||||
input logic sel
|
||||
,output logic val
|
||||
);
|
||||
|
||||
logic l0;
|
||||
|
||||
always_comb begin
|
||||
l0 = 1'b0;
|
||||
if (sel) begin
|
||||
l0 = C::ret1();
|
||||
end
|
||||
end
|
||||
|
||||
assign val = l0;
|
||||
|
||||
endmodule
|
||||
|
||||
module m_tb#()();
|
||||
|
||||
logic sel, val;
|
||||
|
||||
mod m(
|
||||
.sel(sel)
|
||||
,.val(val)
|
||||
);
|
||||
|
||||
initial begin
|
||||
#1;
|
||||
sel = 'b0;
|
||||
#1;
|
||||
`checkd(val, 1'b0);
|
||||
sel = 'b1;
|
||||
#1;
|
||||
`checkd(val, 1'b1);
|
||||
sel = 'b0;
|
||||
#1;
|
||||
`checkd(val, 1'b0);
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue