diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp
index ace0eff89..39aa49a8d 100644
--- a/src/V3Tristate.cpp
+++ b/src/V3Tristate.cpp
@@ -1645,7 +1645,8 @@ class TristateVisitor final : public TristateBaseVisitor {
             AstPin* const enpinp
                 = new AstPin{nodep->fileline(), nodep->pinNum(),
                              enModVarp->name(),  // should be {var}"__en"
-                             new AstVarRef{nodep->fileline(), enVarp, VAccess::WRITE}};
+                             new AstVarRef{nodep->fileline(), enVarp,
+                                           inDeclProcessing ? VAccess::READ : VAccess::WRITE}};
             enpinp->modVarp(enModVarp);
             UINFO(9, "       newpin " << enpinp);
             enpinp->user2Or(U2_BOTH);  // don't iterate the pin later
diff --git a/test_regress/t/t_altera_lpm_bustri_noinl.py b/test_regress/t/t_altera_lpm_bustri_noinl.py
new file mode 100644
index 000000000..ff6f6e705
--- /dev/null
+++ b/test_regress/t/t_altera_lpm_bustri_noinl.py
@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t/t_altera_lpm.v"
+module = re.sub(r'.*t_altera_', '', test.name)
+module = re.sub(r'_noinl', '', module)
+
+test.compile(verilator_flags2=["--top-module", module, "-fno-inline"])
+
+test.passes()