Fix internal error on non-inlined inout pins.

Changes

@@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Throw UNUSED/UNDRIVEN only once per net in a parametrized module.
 
+**** Fix internal error on non-inlined inout pins.  [Jeff Winston]
+
 **** Fix false BLKSEQ on non-unrolled for loop indexes.  [Jeff Winston]
 
 **** Fix block comment not separating identifiers, bug311. [Gene Sullivan]

src/V3AstNodes.h

@@ -912,7 +912,9 @@ public:
 	,m_name(name), m_svImplicit(false) {
 	m_pinNum = pinNum;
 	m_modVarp = NULL;
-	setNOp1p(exprp); }
+	setNOp1p(exprp);
+	if (exprp) widthSignedFrom(exprp);
+    }
     ASTNODE_NODE_FUNCS(Pin, PIN)
     virtual void dump(ostream& str);
     virtual bool broken() const { return (m_modVarp && !m_modVarp->brokeExists()); }

test_regress/t/t_EXAMPLE.v

@@ -13,7 +13,7 @@
 // please note it here, otherwise:**
 //
 // This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2010 by Wilson Snyder.
+// without warranty, 2011 by Wilson Snyder.
 
 module t (/*AUTOARG*/
    // Inputs

test_regress/t/t_tri_dangle.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_tri_dangle.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inouts
+   AVDD, AVSS
+   );
+   inout AVDD;
+   inout  AVSS;
+
+   sub sub (/*AUTOINST*/
+	    // Inouts
+	    .AVDD			(AVDD),
+	    .AVSS			(AVSS));
+
+   initial begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+   end
+endmodule
+
+module sub (/*AUTOARG*/
+   // Inouts
+   AVDD, AVSS
+   );
+   // verilator no_inline_module
+   inout AVDD;
+   inout AVSS;
+endmodule