mirror of
https://github.com/verilator/verilator.git
synced 2026-10-02 16:13:34 +02:00
This commit is contained in:
Wilson Snyder
@@ -154,7 +154,6 @@ Verilator 5.053 devel
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* Fix stack depth calculations over calls (#8544). [Nick Brereton]
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* Fix cascading errors after unsupported class dot reference in parameter value (#8551). [Martijn Wobbes, Antmicro Ltd.]
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* Fix vpi_put_value crash on NULL value pointer (#8553). [Nick Brereton]
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* Fix --hierarchical parameter specialization name collisions (#8555). [Marco Bartoli]
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* Fix dehash of a suffix after a hashed name (#8556). [Ethan Sifferman]
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+31
-33
@@ -57,6 +57,7 @@
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#include "V3Case.h"
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#include "V3Const.h"
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#include "V3EmitV.h"
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#include "V3Hasher.h"
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#include "V3LinkDotIfaceCapture.h"
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#include "V3MemberMap.h"
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#include "V3Os.h"
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@@ -71,7 +72,6 @@
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#include <deque>
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#include <map>
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#include <memory>
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#include <set>
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#include <unordered_map>
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#include <vector>
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@@ -281,7 +281,7 @@ class ParamProcessor final {
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std::map<const std::string, std::string>
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m_longMap; // Hash of very long names to unique identity number
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std::set<std::string> m_longSuffixes; // Digest suffixes used by m_longMap
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int m_longId = 0;
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// All module names that are loaded from source code
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// Generated modules by this visitor is not included
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@@ -290,13 +290,8 @@ class ParamProcessor final {
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CloneMap m_originalParams; // Map between parameters of copied parameteized classes and their
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// original nodes
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std::map<const std::string, std::string> m_valueNames; // Parameter value text to its name
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std::set<std::string> m_valueSuffixes; // Digest suffixes used by m_valueNames
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// Number of digest hex digits in a name. With 8 digits, a collision between names made in
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// different runs, such as those of different hierarchical blocks, is unlikely. Within one
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// run, digestSuffix resolves a collision by lengthening the later text's suffix, which can
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// then differ between runs.
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static constexpr std::string::size_type DIGEST_DIGITS = 8;
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std::map<const V3Hash, int> m_valueMap; // Hash of node hash to param value
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int m_nextValue = 1; // Next value to use in m_valueMap
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const AstNodeModule* m_modp = nullptr; // Current module being processed
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@@ -397,12 +392,11 @@ class ParamProcessor final {
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key += "] ";
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key += paramValueString(dtypep->subDTypep());
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} else if (const AstInitArray* const initp = VN_CAST(nodep, InitArray)) {
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// Include the indices and the default, as with a default the map may be sparse
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key += "{";
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for (const auto& it : initp->map()) {
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key += cvtToStr(it.first) + ":" + paramValueString(it.second->valuep()) + ",";
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for (auto it : initp->map()) {
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key += paramValueString(it.second->valuep());
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key += ",";
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}
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if (initp->defaultp()) key += "default:" + paramValueString(initp->defaultp()) + ",";
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key += "}";
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} else if (const AstConsPackUOrStruct* const structp = VN_CAST(nodep, ConsPackUOrStruct)) {
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key += "{";
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@@ -452,39 +446,43 @@ class ParamProcessor final {
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return key;
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}
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// Return a name suffix for 'text' from its SHA-512 digest. Hierarchical blocks are
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// Verilated in separate runs, where a counter would restart, but the digest is the same in
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// every run. Use the shortest digest prefix of at least DIGEST_DIGITS digits that is not
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// already in 'usedr', and add it to 'usedr'.
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static string digestSuffix(const string& text, std::set<string>& usedr) {
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const string hex = VHashSha512{text}.digestHex();
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// Force collisions of the prefixes -- for testing only
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string::size_type digits = v3Global.opt.debugCollision() ? 1 : DIGEST_DIGITS;
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while (digits < hex.size() && !usedr.insert(hex.substr(0, digits)).second) ++digits;
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return hex.substr(0, digits);
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}
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string paramValueNumber(AstNode* nodep) {
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// For type parameters (NodeDType), use only the string representation for hashing.
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// Using V3Hasher::uncachedHash includes AST node pointer which differs for equivalent
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// types represented by different AST nodes (e.g., parameterized class specializations).
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// For value parameters, we can still use the AST hash for better collision resistance.
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// All call sites resolve through skipRefToNonRefp() or pass non-DType
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// nodes, so nodep should never be a bare RefDType here.
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if (VN_IS(nodep, RefDType)) { // LCOV_EXCL_LINE
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nodep->v3fatalSrc("Unexpected RefDType in paramValueNumber"); // LCOV_EXCL_LINE
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}
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// Name the value by its text, which is the same for equal values or types in every run.
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// V3Hasher is unsuitable, as it hashes node pointers, which can differ for equal types.
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// V3Hash of a string is unsuitable, as std::hash varies between C++ libraries.
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const string text = paramValueString(nodep);
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const auto pair = m_valueNames.emplace(text, "");
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if (pair.second) pair.first->second = "z" + digestSuffix(text, m_valueSuffixes);
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return pair.first->second;
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const string paramStr = paramValueString(nodep);
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V3Hash hash;
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if (VN_IS(nodep, NodeDType)) {
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// Type parameter: use only string-based hash for type equivalence
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hash = V3Hash{paramStr};
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} else {
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// Value parameter: use AST hash + string for better collision resistance
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hash = V3Hasher::uncachedHash(nodep) + paramStr;
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}
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// Force hash collisions -- for testing only
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// cppcheck-suppress unreadVariable
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if (VL_UNLIKELY(v3Global.opt.debugCollision())) hash = V3Hash{paramStr};
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int num;
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const auto pair = m_valueMap.emplace(hash, 0);
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if (pair.second) pair.first->second = m_nextValue++;
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num = pair.first->second;
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return "z"s + cvtToStr(num);
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}
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string moduleCalcName(const AstNodeModule* srcModp, const string& longname) {
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string newname = longname;
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if (longname.length() > 30) {
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const auto pair = m_longMap.emplace(longname, "");
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if (pair.second) {
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newname = srcModp->name();
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// We use all upper case above, so lower here can't conflict
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pair.first->second
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= srcModp->name() + "__pi" + digestSuffix(longname, m_longSuffixes);
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newname += "__pi" + cvtToStr(++m_longId);
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pair.first->second = newname;
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}
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newname = pair.first->second;
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}
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@@ -1,4 +1,4 @@
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%Error: t/t_class_param_enum_bad.v:25:40: Assign RHS expects a CLASSREFDTYPE 'Converter__Tz7d09f080', got CLASSREFDTYPE 'Converter__Tza32c8cf8'
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%Error: t/t_class_param_enum_bad.v:25:40: Assign RHS expects a CLASSREFDTYPE 'Converter__Tz2', got CLASSREFDTYPE 'Converter__Tz1'
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: ... note: In instance 't'
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25 | automatic Converter #(bit) conv2 = conv1;
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| ^~~~~
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@@ -1,18 +0,0 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.compile(verilator_flags2=['--binary', '--hierarchical'])
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test.execute()
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test.passes()
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@@ -1,111 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Specializations of a parameterized class are distinct types, but for matching ones, and
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// $typename returns their names (IEEE 1800-2023 8.25, 20.6.1). Hierarchical block 'hb' and the
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// parent are Verilated in runs of their own, which each name the specializations they elaborate:
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// a specialization has one name in both, and distinct ones distinct names. hb elaborates two
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// specializations of each class, and passes their names to the parent, which elaborates the
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// second of those.
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// A type name as characters, the first the most significant, for a port to pass
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localparam int NAME_CHARS = 64;
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function automatic logic [8*NAME_CHARS-1:0] to_bits(string name);
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to_bits = '0;
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for (int i = 0; i < name.len() && i < NAME_CHARS; ++i) to_bits[8*(NAME_CHARS-1-i)+:8] = name[i];
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endfunction
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function automatic string to_name(logic [8*NAME_CHARS-1:0] name_bits);
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to_name = "";
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for (int i = 0; i < NAME_CHARS; ++i) begin
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if (name_bits[8*(NAME_CHARS-1-i)+:8] == 0) break;
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to_name = {to_name, string'(name_bits[8*(NAME_CHARS-1-i)+:8])};
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end
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endfunction
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// Of a type parameter
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class TypeParam #(
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type T = int
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);
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T v;
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endclass
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// Of a parameter not of 32 bits
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class ByteParam #(
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bit [7:0] B = 8'd1
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);
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bit [7:0] v = B;
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endclass
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// Of parameters whose values make a long name
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class LongParameters #(
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int FIRST_PARAMETER = 1,
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int SECOND_PARAMETER = 2
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);
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int v = FIRST_PARAMETER + SECOND_PARAMETER;
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endclass
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module hb (
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output logic [8*NAME_CHARS-1:0] type_a_name,
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output logic [8*NAME_CHARS-1:0] type_b_name,
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output logic [8*NAME_CHARS-1:0] byte_a_name,
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output logic [8*NAME_CHARS-1:0] byte_b_name,
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output logic [8*NAME_CHARS-1:0] long_a_name,
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output logic [8*NAME_CHARS-1:0] long_b_name
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);
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/*verilator hier_block*/
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TypeParam #(byte) type_a;
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TypeParam #(shortint) type_b;
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ByteParam #(8'd2) byte_a;
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ByteParam #(8'd3) byte_b;
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LongParameters #(1111111, 2222222) long_a;
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LongParameters #(3333333, 4444444) long_b;
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// In a procedure, as the handles are dynamic (IEEE 1800-2023 6.21)
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initial begin
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type_a_name = to_bits($typename(type_a));
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type_b_name = to_bits($typename(type_b));
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byte_a_name = to_bits($typename(byte_a));
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byte_b_name = to_bits($typename(byte_b));
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long_a_name = to_bits($typename(long_a));
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long_b_name = to_bits($typename(long_b));
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end
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endmodule
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module t;
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logic [8*NAME_CHARS-1:0] type_a_name;
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logic [8*NAME_CHARS-1:0] type_b_name;
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logic [8*NAME_CHARS-1:0] byte_a_name;
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logic [8*NAME_CHARS-1:0] byte_b_name;
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logic [8*NAME_CHARS-1:0] long_a_name;
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logic [8*NAME_CHARS-1:0] long_b_name;
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TypeParam #(shortint) type_b;
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ByteParam #(8'd3) byte_b;
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LongParameters #(3333333, 4444444) long_b;
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hb h (.*);
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// Without $finish, which could come before hb's names: the simulation ends, and runs the final
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// blocks, once time zero has run
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final begin
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// A specialization of both has one name in both
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`checks(to_name(type_b_name), $typename(type_b));
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`checks(to_name(byte_b_name), $typename(byte_b));
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`checks(to_name(long_b_name), $typename(long_b));
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// Distinct specializations have distinct names
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`checkd(to_name(type_a_name) != $typename(type_b), 1);
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`checkd(to_name(byte_a_name) != $typename(byte_b), 1);
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`checkd(to_name(long_a_name) != $typename(long_b), 1);
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$write("*-* All Finished *-*\n");
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end
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endmodule
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@@ -1,4 +1,4 @@
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%Error: t/t_mailbox_bad.v:12:11: Class method 'bad_method' not found in class 'mailbox__Tz6d8d043b'
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%Error: t/t_mailbox_bad.v:12:11: Class method 'bad_method' not found in class 'mailbox__Tz1'
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: ... note: In instance 't'
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12 | if (m.bad_method() != 0) $stop;
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| ^~~~~~~~~~
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@@ -1,18 +0,0 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--binary'])
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test.execute()
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test.passes()
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@@ -1,46 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Unpacked array parameter values with equal elements at different indices are different
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// values, so the instances given them must not share a module specialization.
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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typedef int arr_t[4];
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// Sets one element only, so the constant value has that element and a default for the others
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function automatic arr_t one_hot(int idx);
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one_hot[idx] = 5;
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endfunction
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module sub #(
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parameter arr_t ARR = '{default: 0}
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) (
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output arr_t o
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);
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assign o = ARR;
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endmodule
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module t;
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arr_t o1;
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arr_t o2;
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sub #(.ARR(one_hot(1))) u1 (.o(o1));
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sub #(.ARR(one_hot(2))) u2 (.o(o2));
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// Without $finish, which could come before the outputs: the simulation ends, and runs the final
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// blocks, once time zero has run
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final begin
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`checkd(o1[1], 5);
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`checkd(o1[2], 0);
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`checkd(o2[1], 0);
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`checkd(o2[2], 5);
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$write("*-* All Finished *-*\n");
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end
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endmodule
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@@ -1,11 +1,11 @@
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%Error-UNSUPPORTED: t/t_timing_at_dtype_bad.v:20:12: Unsupported: Cannot detect changes on expression of complex type 'int$[$]'
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: ... note: In instance 't::any_monitor__pif994bd0b'
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: ... note: In instance 't::any_monitor__Tz1_TBz1'
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: ... May be caused by combinational cycles reported with UNOPTFLAT
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20 | @req;
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| ^~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_timing_at_dtype_bad.v:23:12: Unsupported: Cannot detect changes on expression of complex type 'int$[$]'
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: ... note: In instance 't::any_monitor__pif994bd0b'
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: ... note: In instance 't::any_monitor__Tz1_TBz1'
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: ... May be caused by combinational cycles reported with UNOPTFLAT
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23 | @rsp;
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| ^~~
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