From dc43071f1c455f6ef4c6b159d7bd2231e6d59844 Mon Sep 17 00:00:00 2001 From: Ethan Sifferman Date: Sat, 11 Jan 2025 19:53:11 -0800 Subject: [PATCH] Improve `resetall support (#5728) (#5730) --- src/verilog.l | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/verilog.l b/src/verilog.l index b1a536557..5aa52e4ed 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -1062,7 +1062,11 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "`protect" { FL_FWD; FL_BRK; } "`remove_gatenames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility "`remove_netnames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility - "`resetall" { FL; PARSEP->lexFileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true); + "`resetall" { FL; + PARSEP->lexFileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true); + v3Global.rootp()->timeInit(); + PARSEP->lexFileline()->celldefineOn(false); + PARSEP->unconnectedDrive(VOptionBool::OPT_DEFAULT_FALSE); return yaT_RESETALL; } // Rest handled by preproc "`suppress_faults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility "`timescale"{ws}+[^\n\r]* { FL; PARSEP->lexTimescaleParse(yylval.fl,