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verilator
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This commit is contained in:
Todd Strader 2026-07-01 12:58:59 -04:00
parent ab53dad0ba
commit d85f04ec4b
7 changed files with 60 additions and 60 deletions
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14
test_regress/t/t_vlt_public_spec_hier_cellarr_share.v
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@ -9,15 +9,15 @@
// arrayed cells. // arrayed cells.
module sub(); module sub();
int leaf = 0; int leaf = 0;
endmodule endmodule
module top(); module top();
sub i_sub [1:0] (); sub i_sub [1:0] ();
initial begin initial begin
$c("Verilated::scopesDump();"); $c("Verilated::scopesDump();");
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule

16
test_regress/t/t_vlt_public_spec_hier_escid.v
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@ -6,16 +6,16 @@
module sub_mod(); module sub_mod();
int \var.with.dot = 0; int \var.with.dot = 0;
endmodule endmodule
module top(); module top();
sub_mod \inst.with.dot (); sub_mod \inst.with.dot ();
sub_mod \foo[abc] (); sub_mod \foo[abc] ();
initial begin initial begin
$c("Verilated::scopesDump();"); $c("Verilated::scopesDump();");
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule

14
test_regress/t/t_vlt_public_spec_hier_escid_array.v
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@ -6,15 +6,15 @@
module sub(); module sub();
int leaf = 0; int leaf = 0;
endmodule endmodule
module top(); module top();
sub \foo] [3:0] (); sub \foo] [3:0] ();
initial begin initial begin
$c("Verilated::scopesDump();"); $c("Verilated::scopesDump();");
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule

18
test_regress/t/t_vlt_public_spec_hier_iface.v
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@ -6,17 +6,17 @@
interface ifc(); interface ifc();
logic [7:0] data; logic [7:0] data;
endinterface endinterface
module top(); module top();
ifc i_single (); ifc i_single ();
ifc i_arr [2:0] (); ifc i_arr [2:0] ();
ifc i_md [1:0][1:0] (); ifc i_md [1:0][1:0] ();
initial begin initial begin
$c("Verilated::scopesDump();"); $c("Verilated::scopesDump();");
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule

14
test_regress/t/t_vlt_public_spec_hier_multidim.v
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@ -6,15 +6,15 @@
module sub(); module sub();
int leaf = 0; int leaf = 0;
endmodule endmodule
module top(); module top();
sub i_sub [1:0][1:0] (); sub i_sub [1:0][1:0] ();
initial begin initial begin
$c("Verilated::scopesDump();"); $c("Verilated::scopesDump();");
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule

24
test_regress/t/t_vlt_public_spec_hier_negidx.v
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@ -6,21 +6,21 @@
module sub(); module sub();
int sub_leaf = 0; int sub_leaf = 0;
endmodule endmodule
module top(); module top();
generate generate
for (genvar i = -2; i < 0; ++i) begin : gen_loop for (genvar i = -2; i < 0; ++i) begin : gen_loop
int loop_local; int loop_local;
end end
endgenerate endgenerate
sub i_sub [0:-2] (); sub i_sub [0:-2] ();
initial begin initial begin
$c("Verilated::scopesDump();"); $c("Verilated::scopesDump();");
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule

20
test_regress/t/t_vlt_public_spec_hier_share.v
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@ -6,18 +6,18 @@
module sub(); module sub();
int some_var = 0; int some_var = 0;
endmodule endmodule
module top(); module top();
sub sub_a (); // tagged public_flat sub sub_a (); // tagged public_flat
sub sub_b (); // tagged public_flat (same marking as sub_a -> shares clone) sub sub_b (); // tagged public_flat (same marking as sub_a -> shares clone)
sub sub_c (); // tagged public_flat_rd (different marking -> own clone) sub sub_c (); // tagged public_flat_rd (different marking -> own clone)
sub sub_d (); // not tagged sub sub_d (); // not tagged
initial begin initial begin
$c("Verilated::scopesDump();"); $c("Verilated::scopesDump();");
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule