diff --git a/test_regress/t/t_vlt_public_spec_hier_cellarr_share.v b/test_regress/t/t_vlt_public_spec_hier_cellarr_share.v
index 3b5f1cf8d..fea2c8db0 100644
--- a/test_regress/t/t_vlt_public_spec_hier_cellarr_share.v
+++ b/test_regress/t/t_vlt_public_spec_hier_cellarr_share.v
@@ -9,15 +9,15 @@
 // arrayed cells.
 
 module sub();
-   int leaf = 0;
+  int leaf = 0;
 endmodule
 
 module top();
-   sub i_sub [1:0] ();
+  sub i_sub [1:0] ();
 
-   initial begin
-      $c("Verilated::scopesDump();");
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  initial begin
+    $c("Verilated::scopesDump();");
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule
diff --git a/test_regress/t/t_vlt_public_spec_hier_escid.v b/test_regress/t/t_vlt_public_spec_hier_escid.v
index 57f3e168e..5c073670e 100644
--- a/test_regress/t/t_vlt_public_spec_hier_escid.v
+++ b/test_regress/t/t_vlt_public_spec_hier_escid.v
@@ -6,16 +6,16 @@
 
 
 module sub_mod();
-   int \var.with.dot = 0;
+  int \var.with.dot = 0;
 endmodule
 
 module top();
-   sub_mod \inst.with.dot ();
-   sub_mod \foo[abc] ();
+  sub_mod \inst.with.dot ();
+  sub_mod \foo[abc] ();
 
-   initial begin
-      $c("Verilated::scopesDump();");
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  initial begin
+    $c("Verilated::scopesDump();");
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule
diff --git a/test_regress/t/t_vlt_public_spec_hier_escid_array.v b/test_regress/t/t_vlt_public_spec_hier_escid_array.v
index 9b36001b1..a286e29e9 100644
--- a/test_regress/t/t_vlt_public_spec_hier_escid_array.v
+++ b/test_regress/t/t_vlt_public_spec_hier_escid_array.v
@@ -6,15 +6,15 @@
 
 
 module sub();
-   int leaf = 0;
+  int leaf = 0;
 endmodule
 
 module top();
-   sub \foo] [3:0] ();
+  sub \foo] [3:0] ();
 
-   initial begin
-      $c("Verilated::scopesDump();");
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  initial begin
+    $c("Verilated::scopesDump();");
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule
diff --git a/test_regress/t/t_vlt_public_spec_hier_iface.v b/test_regress/t/t_vlt_public_spec_hier_iface.v
index 311e23a9a..03b741846 100644
--- a/test_regress/t/t_vlt_public_spec_hier_iface.v
+++ b/test_regress/t/t_vlt_public_spec_hier_iface.v
@@ -6,17 +6,17 @@
 
 
 interface ifc();
-   logic [7:0] data;
+  logic [7:0] data;
 endinterface
 
 module top();
-   ifc i_single ();
-   ifc i_arr [2:0] ();
-   ifc i_md [1:0][1:0] ();
+  ifc i_single ();
+  ifc i_arr [2:0] ();
+  ifc i_md [1:0][1:0] ();
 
-   initial begin
-      $c("Verilated::scopesDump();");
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  initial begin
+    $c("Verilated::scopesDump();");
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule
diff --git a/test_regress/t/t_vlt_public_spec_hier_multidim.v b/test_regress/t/t_vlt_public_spec_hier_multidim.v
index d500d97ad..f2a1b0a48 100644
--- a/test_regress/t/t_vlt_public_spec_hier_multidim.v
+++ b/test_regress/t/t_vlt_public_spec_hier_multidim.v
@@ -6,15 +6,15 @@
 
 
 module sub();
-   int leaf = 0;
+  int leaf = 0;
 endmodule
 
 module top();
-   sub i_sub [1:0][1:0] ();
+  sub i_sub [1:0][1:0] ();
 
-   initial begin
-      $c("Verilated::scopesDump();");
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  initial begin
+    $c("Verilated::scopesDump();");
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule
diff --git a/test_regress/t/t_vlt_public_spec_hier_negidx.v b/test_regress/t/t_vlt_public_spec_hier_negidx.v
index 43cd9306c..3dd4429e3 100644
--- a/test_regress/t/t_vlt_public_spec_hier_negidx.v
+++ b/test_regress/t/t_vlt_public_spec_hier_negidx.v
@@ -6,21 +6,21 @@
 
 
 module sub();
-   int sub_leaf = 0;
+  int sub_leaf = 0;
 endmodule
 
 module top();
-   generate
-      for (genvar i = -2; i < 0; ++i) begin : gen_loop
-         int loop_local;
-      end
-   endgenerate
+  generate
+    for (genvar i = -2; i < 0; ++i) begin : gen_loop
+      int loop_local;
+    end
+  endgenerate
 
-   sub i_sub [0:-2] ();
+  sub i_sub [0:-2] ();
 
-   initial begin
-      $c("Verilated::scopesDump();");
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  initial begin
+    $c("Verilated::scopesDump();");
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule
diff --git a/test_regress/t/t_vlt_public_spec_hier_share.v b/test_regress/t/t_vlt_public_spec_hier_share.v
index 8d333ad8c..6b67d131c 100644
--- a/test_regress/t/t_vlt_public_spec_hier_share.v
+++ b/test_regress/t/t_vlt_public_spec_hier_share.v
@@ -6,18 +6,18 @@
 
 
 module sub();
-   int some_var = 0;
+  int some_var = 0;
 endmodule
 
 module top();
-   sub sub_a ();   // tagged public_flat
-   sub sub_b ();   // tagged public_flat (same marking as sub_a -> shares clone)
-   sub sub_c ();   // tagged public_flat_rd (different marking -> own clone)
-   sub sub_d ();   // not tagged
+  sub sub_a ();   // tagged public_flat
+  sub sub_b ();   // tagged public_flat (same marking as sub_a -> shares clone)
+  sub sub_c ();   // tagged public_flat_rd (different marking -> own clone)
+  sub sub_d ();   // not tagged
 
-   initial begin
-      $c("Verilated::scopesDump();");
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+  initial begin
+    $c("Verilated::scopesDump();");
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule