[#73220] add t_trace_array_saif tests
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(SAIFILE
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(SAIFVERSION "2.0")
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(DIRECTION "backward")
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(DESIGN "t")
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(DESIGN "foo")
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(PROGRAM_NAME "Verilator")
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(VERSION "5.032")
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(DIVIDER / )
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(TIMESCALE 1 ps)
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(DURATION 59)
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(INSTANCE top
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(TIMESCALE 1ps)
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(DURATION 60)
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(INSTANCE top
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(NET
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(clk (T0 35) (T1 25) (TX 0) (TC 11))
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(clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
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)
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(INSTANCE t
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(NET
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(clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
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(cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
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(cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
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)
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(INSTANCE biggie
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(NET
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(clk (T0 35) (T1 25) (TX 0) (TC 11))
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(cyc\[0\] (T0 30) (T1 30) (TX 0) (TC 6))
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(cyc\[1\] (T0 40) (T1 20) (TX 0) (TC 3))
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(cyc\[2\] (T0 40) (T1 20) (TX 0) (TC 1))
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)
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(INSTANCE biggie
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(NET
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(d\[1\] (T0 50) (T1 10) (TX 0) (TC 2))
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(d\[2\] (T0 50) (T1 10) (TX 0) (TC 2))
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(d\[3\] (T0 40) (T1 20) (TX 0) (TC 4))
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(d\[4\] (T0 40) (T1 20) (TX 0) (TC 4))
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(d\[5\] (T0 30) (T1 30) (TX 0) (TC 6))
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(d\[6\] (T0 40) (T1 20) (TX 0) (TC 5))
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(d\[7\] (T0 30) (T1 30) (TX 0) (TC 6))
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(d\[8\] (T0 40) (T1 20) (TX 0) (TC 5))
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(d\[9\] (T0 40) (T1 20) (TX 0) (TC 4))
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(d\[10\] (T0 50) (T1 10) (TX 0) (TC 3))
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(d\[11\] (T0 50) (T1 10) (TX 0) (TC 2))
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(d\[12\] (T0 60) (T1 0) (TX 0) (TC 1))
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)
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(d\[1\] (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2))
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(d\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
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(d\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
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(d\[4\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
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(d\[5\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
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(d\[6\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[7\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[8\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[9\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 4))
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(d\[10\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 4))
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(d\[11\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
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(d\[12\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
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(d\[13\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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(d\[14\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[15\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 2))
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(d\[16\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
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(d\[17\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
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(d\[18\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[19\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[20\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[21\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
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(d\[22\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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(d\[23\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[24\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[25\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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(d\[26\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[27\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[28\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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(d\[29\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 2))
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(d\[30\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
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(d\[31\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
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(d\[32\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
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(d\[33\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
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(d\[34\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
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(d\[35\] (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
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(d\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
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)
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)
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)
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)
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)
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)
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@ -0,0 +1,22 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.top_filename = "t/t_trace_array.v"
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test.golden_filename = "t/t_trace_array_saif.out"
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test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2 --trace-structs'])
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test.execute()
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test.saif_identical(test.trace_filename, test.golden_filename)
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test.passes()
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