From d61e88bbe9ed455e8a598e5b7a058f8b69783271 Mon Sep 17 00:00:00 2001 From: Mateusz Gancarz Date: Tue, 25 Feb 2025 15:27:36 +0100 Subject: [PATCH] [#73220] add t_trace_array_saif tests --- test_regress/t/t_trace_array_saif.out | 78 ++++++++++++------- .../t/t_trace_array_saif_threads_2.py | 22 ++++++ 2 files changed, 74 insertions(+), 26 deletions(-) create mode 100755 test_regress/t/t_trace_array_saif_threads_2.py diff --git a/test_regress/t/t_trace_array_saif.out b/test_regress/t/t_trace_array_saif.out index 94e14405a..69072ed77 100644 --- a/test_regress/t/t_trace_array_saif.out +++ b/test_regress/t/t_trace_array_saif.out @@ -1,37 +1,63 @@ (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") -(DESIGN "t") +(DESIGN "foo") +(PROGRAM_NAME "Verilator") +(VERSION "5.032") (DIVIDER / ) -(TIMESCALE 1 ps) -(DURATION 59) -(INSTANCE top +(TIMESCALE 1ps) +(DURATION 60) + (INSTANCE top (NET - (clk (T0 35) (T1 25) (TX 0) (TC 11)) + (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) ) (INSTANCE t + (NET + (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) + (cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) + (cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) + (cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) + ) + (INSTANCE biggie (NET - (clk (T0 35) (T1 25) (TX 0) (TC 11)) - (cyc\[0\] (T0 30) (T1 30) (TX 0) (TC 6)) - (cyc\[1\] (T0 40) (T1 20) (TX 0) (TC 3)) - (cyc\[2\] (T0 40) (T1 20) (TX 0) (TC 1)) - ) - (INSTANCE biggie - (NET - (d\[1\] (T0 50) (T1 10) (TX 0) (TC 2)) - (d\[2\] (T0 50) (T1 10) (TX 0) (TC 2)) - (d\[3\] (T0 40) (T1 20) (TX 0) (TC 4)) - (d\[4\] (T0 40) (T1 20) (TX 0) (TC 4)) - (d\[5\] (T0 30) (T1 30) (TX 0) (TC 6)) - (d\[6\] (T0 40) (T1 20) (TX 0) (TC 5)) - (d\[7\] (T0 30) (T1 30) (TX 0) (TC 6)) - (d\[8\] (T0 40) (T1 20) (TX 0) (TC 5)) - (d\[9\] (T0 40) (T1 20) (TX 0) (TC 4)) - (d\[10\] (T0 50) (T1 10) (TX 0) (TC 3)) - (d\[11\] (T0 50) (T1 10) (TX 0) (TC 2)) - (d\[12\] (T0 60) (T1 0) (TX 0) (TC 1)) - ) + (d\[1\] (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) + (d\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) + (d\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2)) + (d\[4\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2)) + (d\[5\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2)) + (d\[6\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[7\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[8\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[9\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 4)) + (d\[10\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 4)) + (d\[11\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5)) + (d\[12\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5)) + (d\[13\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4)) + (d\[14\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[15\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 2)) + (d\[16\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) + (d\[17\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) + (d\[18\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[19\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[20\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[21\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5)) + (d\[22\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4)) + (d\[23\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[24\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[25\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4)) + (d\[26\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[27\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[28\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) + (d\[29\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 2)) + (d\[30\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) + (d\[31\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) + (d\[32\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) + (d\[33\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) + (d\[34\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) + (d\[35\] (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) + (d\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) ) + ) ) -) + ) ) diff --git a/test_regress/t/t_trace_array_saif_threads_2.py b/test_regress/t/t_trace_array_saif_threads_2.py new file mode 100755 index 000000000..11e1015b2 --- /dev/null +++ b/test_regress/t/t_trace_array_saif_threads_2.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_array.v" +test.golden_filename = "t/t_trace_array_saif.out" + +test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2 --trace-structs']) + +test.execute() + +test.saif_identical(test.trace_filename, test.golden_filename) + +test.passes()