Fix crash in unroller on increment-only while loops.

This commit is contained in:
Wilson Snyder 2020-05-10 15:26:41 -04:00
parent a2cc053c6f
commit d4a631446b
3 changed files with 46 additions and 2 deletions

View File

@ -389,6 +389,7 @@ private:
if (nodep->backp()->nextp() == nodep) initp = nodep->backp(); if (nodep->backp()->nextp() == nodep) initp = nodep->backp();
// Grab assignment // Grab assignment
AstNode* incp = NULL; // Should be last statement AstNode* incp = NULL; // Should be last statement
AstNode* bodysp = nodep->bodysp();
if (nodep->incsp()) V3Const::constifyEdit(nodep->incsp()); if (nodep->incsp()) V3Const::constifyEdit(nodep->incsp());
// cppcheck-suppress duplicateCondition // cppcheck-suppress duplicateCondition
if (nodep->incsp()) { if (nodep->incsp()) {
@ -397,11 +398,12 @@ private:
for (incp = nodep->bodysp(); incp && incp->nextp(); incp = incp->nextp()) {} for (incp = nodep->bodysp(); incp && incp->nextp(); incp = incp->nextp()) {}
if (incp) VL_DO_DANGLING(V3Const::constifyEdit(incp), incp); if (incp) VL_DO_DANGLING(V3Const::constifyEdit(incp), incp);
// Again, as may have changed // Again, as may have changed
bodysp = nodep->bodysp();
for (incp = nodep->bodysp(); incp && incp->nextp(); incp = incp->nextp()) {} for (incp = nodep->bodysp(); incp && incp->nextp(); incp = incp->nextp()) {}
if (incp == bodysp) bodysp = NULL;
} }
// And check it // And check it
if (forUnrollCheck(nodep, initp, nodep->precondsp(), nodep->condp(), incp, if (forUnrollCheck(nodep, initp, nodep->precondsp(), nodep->condp(), incp, bodysp)) {
nodep->bodysp())) {
VL_DO_DANGLING(pushDeletep(nodep), nodep); // Did replacement VL_DO_DANGLING(pushDeletep(nodep), nodep); // Did replacement
} }
} }

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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2019 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

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@ -0,0 +1,21 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
task main;
integer varintask;
varintask = 0;
while (varintask < 4) begin
varintask = varintask + 1;
end
if (varintask != 4) $stop;
endtask
initial begin
main;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule