diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp
index 3a0191190..19b06ffd5 100644
--- a/src/V3Unroll.cpp
+++ b/src/V3Unroll.cpp
@@ -389,6 +389,7 @@ private:
             if (nodep->backp()->nextp() == nodep) initp = nodep->backp();
             // Grab assignment
             AstNode* incp = NULL;  // Should be last statement
+            AstNode* bodysp = nodep->bodysp();
             if (nodep->incsp()) V3Const::constifyEdit(nodep->incsp());
             // cppcheck-suppress duplicateCondition
             if (nodep->incsp()) {
@@ -397,11 +398,12 @@ private:
                 for (incp = nodep->bodysp(); incp && incp->nextp(); incp = incp->nextp()) {}
                 if (incp) VL_DO_DANGLING(V3Const::constifyEdit(incp), incp);
                 // Again, as may have changed
+                bodysp = nodep->bodysp();
                 for (incp = nodep->bodysp(); incp && incp->nextp(); incp = incp->nextp()) {}
+                if (incp == bodysp) bodysp = NULL;
             }
             // And check it
-            if (forUnrollCheck(nodep, initp, nodep->precondsp(), nodep->condp(), incp,
-                               nodep->bodysp())) {
+            if (forUnrollCheck(nodep, initp, nodep->precondsp(), nodep->condp(), incp, bodysp)) {
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);  // Did replacement
             }
         }
diff --git a/test_regress/t/t_func_inconly.pl b/test_regress/t/t_func_inconly.pl
new file mode 100755
index 000000000..9a15dd2cc
--- /dev/null
+++ b/test_regress/t/t_func_inconly.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_func_inconly.v b/test_regress/t/t_func_inconly.v
new file mode 100644
index 000000000..af4eb9a42
--- /dev/null
+++ b/test_regress/t/t_func_inconly.v
@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+   task main;
+      integer varintask;
+      varintask = 0;
+      while (varintask < 4) begin
+         varintask = varintask + 1;
+      end
+      if (varintask != 4) $stop;
+   endtask
+   initial begin
+      main;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule