Fix type operator for interface signals (#6050) (#6049)

src/V3Param.cpp

@@ -767,6 +767,7 @@ class ParamProcessor final {
             }
         } else if (AstParamTypeDType* const modvarp = pinp->modPTypep()) {
             AstNodeDType* rawTypep = VN_CAST(pinp->exprp(), NodeDType);
+            if (rawTypep) V3Width::widthParamsEdit(rawTypep);
             AstNodeDType* exprp = rawTypep ? rawTypep->skipRefToNonRefp() : nullptr;
             const AstNodeDType* const origp = modvarp->skipRefToNonRefp();
             if (!exprp) {
@@ -945,7 +946,7 @@ class ParamProcessor final {
 
         for (auto* stmtp = srcModpr->stmtsp(); stmtp; stmtp = stmtp->nextp()) {
             if (AstParamTypeDType* dtypep = VN_CAST(stmtp, ParamTypeDType)) {
-                if (VN_IS(dtypep->skipRefp(), VoidDType)) {
+                if (VN_IS(dtypep->skipRefOrNullp(), VoidDType)) {
                     nodep->v3error(
                         "Class parameter type without default value is never given value"
                         << " (IEEE 1800-2023 6.20.1): " << dtypep->prettyNameQ());
@@ -1234,7 +1235,7 @@ class ParamVisitor final : public VNVisitor {
     }
     void visit(AstParamTypeDType* nodep) override {
         iterateChildren(nodep);
-        if (VN_IS(nodep->skipRefp(), VoidDType)) {
+        if (VN_IS(nodep->skipRefOrNullp(), VoidDType)) {
             nodep->v3error("Parameter type without default value is never given value"
                            << " (IEEE 1800-2023 6.20.1): " << nodep->prettyNameQ());
         }

test_regress/t/t_param_type6.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_param_type6.v

@@ -0,0 +1,52 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+interface intf #(
+    parameter type the_type = bit
+);
+    the_type foo;
+endinterface
+
+interface no_param_intf;
+    logic [13:0] bar;
+endinterface
+
+module t (/*AUTOARG*/
+    // Inputs
+    clk
+    );
+
+    input clk;
+
+    intf #(.the_type (logic [7:0])) intf_eight();
+    no_param_intf the_no_param_intf();
+    sub #(.type_bits (8)) sub_eight (
+        .intf_pin (intf_eight),
+        .no_param_intf_pin (the_no_param_intf)
+    );
+
+    // finish report
+    always @ (posedge clk) begin
+        $write("*-* All Finished *-*\n");
+        $finish;
+    end
+endmodule
+
+module sub #(
+    parameter int type_bits
+)(
+    intf intf_pin,
+    no_param_intf no_param_intf_pin
+);
+
+    localparam type intf_type = type(intf_pin.foo);
+    localparam type no_param_intf_type = type(no_param_intf_pin.bar);
+    initial begin
+        if ($bits(intf_type) != type_bits) $stop();
+        if ($bits(no_param_intf_type) != 14) $stop();
+    end
+
+endmodule

test_regress/t/t_type.v

@@ -9,8 +9,12 @@ module t(/*AUTOARG*/);
    real x;
    real y;
    var type(x+y) z;
+   localparam type x_type = type(x);
+   x_type value;
 
    initial begin
+      value = 1.234;
+      if (value != 1.234) $stop();
       x = 1.2;
       y = 2.3;
       z = x + y;
@@ -21,4 +25,23 @@ module t(/*AUTOARG*/);
       $finish;
    end
 
+   localparam type x_minus_y_type = type(x-y);
+   sub_real #(.the_type (x_minus_y_type)) the_sub_real_1();
+   sub_real #(.the_type (type(x-y))) the_sub_real_2();
+   localparam type type1 = type(x*y);
+   type1 type1_var;
+   localparam type type2 = type(type1_var/y);
+   sub_real #(.the_type (type2)) the_sub_real_3();
+
+endmodule
+
+module sub_real #(
+    parameter type the_type = bit
+) ();
+    the_type the_value;
+
+    initial begin
+        the_value = 4.567;
+        if (the_value != 4.567) $stop();
+    end
 endmodule

test_regress/t/t_type_array.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_type_array.v

@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+
+   typedef int arr_t [5];
+   arr_t arr;
+   localparam type arr_type = type(arr);
+   arr_type arr_prime;
+
+   initial begin
+      arr[3] = 123;
+      arr_prime = arr;
+      if (arr_prime[3] != 123) $stop();
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule