Fix wrong filename on include file errors, bug289

This commit is contained in:
Wilson Snyder 2010-09-28 09:33:59 -04:00
parent 16b0c8d353
commit d305a774f0
6 changed files with 53 additions and 7 deletions

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@ -3,6 +3,10 @@ Revision history for Verilator
The contributors that suggested a given feature are shown in []. [by ...]
indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.80****
**** Fix wrong filename on include file errors, bug289. [Brad Parker]
* Verilator 3.804 2010/09/20
*** Support tracing/coverage of underscore signals, bug280. [by Jason McMullan]

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@ -1359,7 +1359,7 @@ int V3PreProcImp::getFinalToken(string& buf) {
if (debug()>=5) fprintf(stderr,"%d: FIN: readjust, fin at %d request at %d\n",
m_lexp->m_tokFilelinep->lineno(),
m_finFilelinep->lineno(), m_lexp->m_tokFilelinep->lineno());
m_finFilelinep = m_finFilelinep->create(m_lexp->m_tokFilelinep->lineno());
m_finFilelinep = m_finFilelinep->create(m_lexp->m_tokFilelinep->filename(),m_lexp->m_tokFilelinep->lineno());
if (outBehind > 0 && outBehind <= (int)V3PreProc::NEWLINES_VS_TICKLINE) {
// Output stream is behind, send newlines to get back in sync
// (Most likely because we're completing a disabled `endif)

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@ -10,10 +10,10 @@
`line 7 "t/t_preproc.v" 0
`line 1 "t/t_preproc_inc2.vh" 1
`line 3 "t/t_preproc.v" 0
`line 3 "t/t_preproc_inc2.vh" 0
`line 4 "t/t_preproc.v" 0
`line 4 "t/t_preproc_inc2.vh" 0
At file "t/t_preproc_inc2.vh" line 4
@ -288,11 +288,11 @@ begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more
`line 180 "t/t_preproc.v" 0
`line 1 "t/t_preproc_inc4.vh" 1
`line 3 "t/t_preproc.v" 0
`line 3 "t/t_preproc_inc4.vh" 0
`line 5 "t/t_preproc.v" 0
`line 5 "t/t_preproc_inc4.vh" 0
`line 7 "t/t_preproc_inc4.vh" 2
@ -612,11 +612,11 @@ hello4hello4hello4hello4
`line 388 "t/t_preproc.v" 0
`line 1 "t/t_preproc_inc4.vh" 1
`line 3 "t/t_preproc.v" 0
`line 3 "t/t_preproc_inc4.vh" 0
`line 5 "t/t_preproc.v" 0
`line 5 "t/t_preproc_inc4.vh" 0
`line 7 "t/t_preproc_inc4.vh" 2

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@ -0,0 +1,21 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
$Self->{vlt} or $Self->skip("Verilator only test");
compile (
verilator_flags2 => ["--lint-only"],
fails=>1,
# The .vh file has the error, not the .v file
expect=>
'%Error: t/t_preproc_inc_inc_bad.vh:10: syntax error, unexpected endmodule, expecting IDENTIFIER'
);
ok(1);
1;

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@ -0,0 +1,11 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
//See bug289
`include "t_preproc_inc_inc_bad.vh"
module t;
endmodule

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@ -0,0 +1,10 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module xx;
xx // intentional error
endmodule