Fix wrong filename on include file errors, bug289
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@ -3,6 +3,10 @@ Revision history for Verilator
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The contributors that suggested a given feature are shown in []. [by ...]
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indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.80****
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**** Fix wrong filename on include file errors, bug289. [Brad Parker]
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* Verilator 3.804 2010/09/20
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*** Support tracing/coverage of underscore signals, bug280. [by Jason McMullan]
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@ -1359,7 +1359,7 @@ int V3PreProcImp::getFinalToken(string& buf) {
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if (debug()>=5) fprintf(stderr,"%d: FIN: readjust, fin at %d request at %d\n",
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m_lexp->m_tokFilelinep->lineno(),
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m_finFilelinep->lineno(), m_lexp->m_tokFilelinep->lineno());
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m_finFilelinep = m_finFilelinep->create(m_lexp->m_tokFilelinep->lineno());
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m_finFilelinep = m_finFilelinep->create(m_lexp->m_tokFilelinep->filename(),m_lexp->m_tokFilelinep->lineno());
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if (outBehind > 0 && outBehind <= (int)V3PreProc::NEWLINES_VS_TICKLINE) {
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// Output stream is behind, send newlines to get back in sync
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// (Most likely because we're completing a disabled `endif)
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@ -10,10 +10,10 @@
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`line 7 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc2.vh" 1
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`line 3 "t/t_preproc.v" 0
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`line 3 "t/t_preproc_inc2.vh" 0
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`line 4 "t/t_preproc.v" 0
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`line 4 "t/t_preproc_inc2.vh" 0
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At file "t/t_preproc_inc2.vh" line 4
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@ -288,11 +288,11 @@ begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more
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`line 180 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc4.vh" 1
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`line 3 "t/t_preproc.v" 0
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`line 3 "t/t_preproc_inc4.vh" 0
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`line 5 "t/t_preproc.v" 0
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`line 5 "t/t_preproc_inc4.vh" 0
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`line 7 "t/t_preproc_inc4.vh" 2
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@ -612,11 +612,11 @@ hello4hello4hello4hello4
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`line 388 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc4.vh" 1
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`line 3 "t/t_preproc.v" 0
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`line 3 "t/t_preproc_inc4.vh" 0
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`line 5 "t/t_preproc.v" 0
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`line 5 "t/t_preproc_inc4.vh" 0
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`line 7 "t/t_preproc_inc4.vh" 2
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@ -0,0 +1,21 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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$Self->{vlt} or $Self->skip("Verilator only test");
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compile (
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verilator_flags2 => ["--lint-only"],
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fails=>1,
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# The .vh file has the error, not the .v file
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expect=>
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'%Error: t/t_preproc_inc_inc_bad.vh:10: syntax error, unexpected endmodule, expecting IDENTIFIER'
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);
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ok(1);
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1;
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@ -0,0 +1,11 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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//See bug289
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`include "t_preproc_inc_inc_bad.vh"
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module t;
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endmodule
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@ -0,0 +1,10 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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module xx;
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xx // intentional error
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endmodule
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