From d305a774f024cefcbca301d84da25774f54dad00 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 28 Sep 2010 09:33:59 -0400 Subject: [PATCH] Fix wrong filename on include file errors, bug289 --- Changes | 4 ++++ src/V3PreProc.cpp | 2 +- test_regress/t/t_preproc.out | 12 ++++++------ test_regress/t/t_preproc_inc_bad.pl | 21 +++++++++++++++++++++ test_regress/t/t_preproc_inc_bad.v | 11 +++++++++++ test_regress/t/t_preproc_inc_inc_bad.vh | 10 ++++++++++ 6 files changed, 53 insertions(+), 7 deletions(-) create mode 100755 test_regress/t/t_preproc_inc_bad.pl create mode 100644 test_regress/t/t_preproc_inc_bad.v create mode 100644 test_regress/t/t_preproc_inc_inc_bad.vh diff --git a/Changes b/Changes index 57e2543bc..779e44fbd 100644 --- a/Changes +++ b/Changes @@ -3,6 +3,10 @@ Revision history for Verilator The contributors that suggested a given feature are shown in []. [by ...] indicates the contributor was also the author of the fix; Thanks! +* Verilator 3.80**** + +**** Fix wrong filename on include file errors, bug289. [Brad Parker] + * Verilator 3.804 2010/09/20 *** Support tracing/coverage of underscore signals, bug280. [by Jason McMullan] diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index 026e562f5..c919525b4 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -1359,7 +1359,7 @@ int V3PreProcImp::getFinalToken(string& buf) { if (debug()>=5) fprintf(stderr,"%d: FIN: readjust, fin at %d request at %d\n", m_lexp->m_tokFilelinep->lineno(), m_finFilelinep->lineno(), m_lexp->m_tokFilelinep->lineno()); - m_finFilelinep = m_finFilelinep->create(m_lexp->m_tokFilelinep->lineno()); + m_finFilelinep = m_finFilelinep->create(m_lexp->m_tokFilelinep->filename(),m_lexp->m_tokFilelinep->lineno()); if (outBehind > 0 && outBehind <= (int)V3PreProc::NEWLINES_VS_TICKLINE) { // Output stream is behind, send newlines to get back in sync // (Most likely because we're completing a disabled `endif) diff --git a/test_regress/t/t_preproc.out b/test_regress/t/t_preproc.out index 8ddb222af..0b6011ebf 100644 --- a/test_regress/t/t_preproc.out +++ b/test_regress/t/t_preproc.out @@ -10,10 +10,10 @@ `line 7 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 -`line 3 "t/t_preproc.v" 0 +`line 3 "t/t_preproc_inc2.vh" 0 -`line 4 "t/t_preproc.v" 0 +`line 4 "t/t_preproc_inc2.vh" 0 At file "t/t_preproc_inc2.vh" line 4 @@ -288,11 +288,11 @@ begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more `line 180 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 -`line 3 "t/t_preproc.v" 0 +`line 3 "t/t_preproc_inc4.vh" 0 -`line 5 "t/t_preproc.v" 0 +`line 5 "t/t_preproc_inc4.vh" 0 `line 7 "t/t_preproc_inc4.vh" 2 @@ -612,11 +612,11 @@ hello4hello4hello4hello4 `line 388 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 -`line 3 "t/t_preproc.v" 0 +`line 3 "t/t_preproc_inc4.vh" 0 -`line 5 "t/t_preproc.v" 0 +`line 5 "t/t_preproc_inc4.vh" 0 `line 7 "t/t_preproc_inc4.vh" 2 diff --git a/test_regress/t/t_preproc_inc_bad.pl b/test_regress/t/t_preproc_inc_bad.pl new file mode 100755 index 000000000..aa3d0eae9 --- /dev/null +++ b/test_regress/t/t_preproc_inc_bad.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +$Self->{vlt} or $Self->skip("Verilator only test"); + +compile ( + verilator_flags2 => ["--lint-only"], + fails=>1, + # The .vh file has the error, not the .v file + expect=> +'%Error: t/t_preproc_inc_inc_bad.vh:10: syntax error, unexpected endmodule, expecting IDENTIFIER' + ); + +ok(1); +1; diff --git a/test_regress/t/t_preproc_inc_bad.v b/test_regress/t/t_preproc_inc_bad.v new file mode 100644 index 000000000..1c8b9ff76 --- /dev/null +++ b/test_regress/t/t_preproc_inc_bad.v @@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +//See bug289 + +`include "t_preproc_inc_inc_bad.vh" + +module t; +endmodule diff --git a/test_regress/t/t_preproc_inc_inc_bad.vh b/test_regress/t/t_preproc_inc_inc_bad.vh new file mode 100644 index 000000000..329c771f3 --- /dev/null +++ b/test_regress/t/t_preproc_inc_inc_bad.vh @@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module xx; + + xx // intentional error + +endmodule