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Verilog format

This commit is contained in:
Veripool API Bot 2026-03-03 07:21:24 -05:00 committed by Wilson Snyder
parent 5821d0697c
commit ce4d35aa85
340 changed files with 7037 additions and 6797 deletions
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11
test_regress/t/t_a1_first_cc.v
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@ -4,15 +4,12 @@
// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-FileCopyrightText: 2017 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
// Test loop // Test loop
always @ (posedge clk) begin always @(posedge clk) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end

8
test_regress/t/t_alias_unsup.v
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@ -51,11 +51,11 @@ module t ( /*AUTOARG*/
// Setup // Setup
crc <= 64'h5aef0c8d_d70a4497; crc <= 64'h5aef0c8d_d70a4497;
sum <= '0; sum <= '0;
end else if (cyc < 10) begin end
else if (cyc < 10) begin
sum <= '0; sum <= '0;
end else end
if (cyc < 90) begin else if (cyc == 99) begin
end else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
`checkh(crc, 64'hc77bb9b3784ea091); `checkh(crc, 64'hc77bb9b3784ea091);
// What checksum will we end up with (above print should match) // What checksum will we end up with (above print should match)

14
test_regress/t/t_array_backw_index_bad.out
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@ -1,29 +1,29 @@
%Error: t/t_array_backw_index_bad.v:17:19: Slice selection '[1:3]' has reversed range order versus data type's '[3:0]' %Error: t/t_array_backw_index_bad.v:17:17: Slice selection '[1:3]' has reversed range order versus data type's '[3:0]'
: ... note: In instance 't' : ... note: In instance 't'
17 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; 17 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2};
| ^ | ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_array_backw_index_bad.v:18:20: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]' %Error: t/t_array_backw_index_bad.v:18:18: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]'
: ... note: In instance 't' : ... note: In instance 't'
18 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; 18 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2};
| ^ | ^
%Error: t/t_array_backw_index_bad.v:19:20: Slice selection '[4:6]' has reversed range order versus data type's '[6:3]' %Error: t/t_array_backw_index_bad.v:19:18: Slice selection '[4:6]' has reversed range order versus data type's '[6:3]'
: ... note: In instance 't' : ... note: In instance 't'
19 | array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; 19 | array_assign2[4:6] = '{32'd4, 32'd3, 32'd2};
| ^ | ^
%Error: t/t_array_backw_index_bad.v:20:21: Slice selection '[6:4]' has reversed range order versus data type's '[3:6]' %Error: t/t_array_backw_index_bad.v:20:19: Slice selection '[6:4]' has reversed range order versus data type's '[3:6]'
: ... note: In instance 't' : ... note: In instance 't'
20 | larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; 20 | larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2};
| ^ | ^
%Error: t/t_array_backw_index_bad.v:22:19: Slice selection index '[4:3]' outside data type's '[3:0]' %Error: t/t_array_backw_index_bad.v:22:17: Slice selection index '[4:3]' outside data type's '[3:0]'
: ... note: In instance 't' : ... note: In instance 't'
22 | array_assign[4:3] = '{32'd4, 32'd3}; 22 | array_assign[4:3] = '{32'd4, 32'd3};
| ^ | ^
%Error: t/t_array_backw_index_bad.v:23:19: Slice selection index '[1:-1]' outside data type's '[3:0]' %Error: t/t_array_backw_index_bad.v:23:17: Slice selection index '[1:-1]' outside data type's '[3:0]'
: ... note: In instance 't' : ... note: In instance 't'
23 | array_assign[1:-1] = '{32'd4, 32'd3}; 23 | array_assign[1:-1] = '{32'd4, 32'd3};
| ^ | ^
%Error: t/t_array_backw_index_bad.v:23:28: Assignment pattern missed initializing elements: -1 %Error: t/t_array_backw_index_bad.v:23:26: Assignment pattern missed initializing elements: -1
: ... note: In instance 't' : ... note: In instance 't'
23 | array_assign[1:-1] = '{32'd4, 32'd3}; 23 | array_assign[1:-1] = '{32'd4, 32'd3};
| ^~ | ^~

8
test_regress/t/t_array_backw_index_bad.v
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@ -6,13 +6,13 @@
module t; module t;
logic [31:0] array_assign [3:0]; logic [31:0] array_assign[3:0];
logic [31:0] larray_assign [0:3]; logic [31:0] larray_assign[0:3];
logic [31:0] array_assign2 [6:3]; logic [31:0] array_assign2[6:3];
logic [31:0] larray_assign2 [3:6]; logic [31:0] larray_assign2[3:6];
initial begin initial begin
array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; array_assign[1:3] = '{32'd4, 32'd3, 32'd2};
larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; larray_assign[3:1] = '{32'd4, 32'd3, 32'd2};

6
test_regress/t/t_array_compare.v
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@ -8,9 +8,9 @@
module t; module t;
reg [3:0] array_1 [2:0]; reg [3:0] array_1[2:0];
reg [3:0] array_2 [2:0]; reg [3:0] array_2[2:0];
reg [3:0] array_3 [3:1]; reg [3:0] array_3[3:1];
reg [3:0] elem; reg [3:0] elem;

12
test_regress/t/t_array_in_struct.v
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@ -7,13 +7,9 @@
//bug991 //bug991
module t; module t;
typedef struct { typedef struct {logic [31:0] arr[3:0];} a_t;
logic [31:0] arr [3:0];
} a_t;
typedef struct { typedef struct {logic [31:0] arr[0:3];} b_t;
logic [31:0] arr [0:3];
} b_t;
a_t array_assign; a_t array_assign;
@ -26,7 +22,7 @@ module t;
array_assign.arr[0] = 32'd1; array_assign.arr[0] = 32'd1;
array_assign.arr[3:1] = '{32'd4, 32'd3, 32'd2}; array_assign.arr[3:1] = '{32'd4, 32'd3, 32'd2};
array_other.arr[0] = array_assign.arr[0]+10; array_other.arr[0] = array_assign.arr[0] + 10;
array_other.arr[3:1] = array_assign.arr[3:1]; array_other.arr[3:1] = array_assign.arr[3:1];
if (array_other.arr[0] != 11) $stop; if (array_other.arr[0] != 11) $stop;
if (array_other.arr[1] != 2) $stop; if (array_other.arr[1] != 2) $stop;
@ -36,7 +32,7 @@ module t;
larray_assign.arr[0] = 32'd1; larray_assign.arr[0] = 32'd1;
larray_assign.arr[1:3] = '{32'd4, 32'd3, 32'd2}; larray_assign.arr[1:3] = '{32'd4, 32'd3, 32'd2};
larray_other.arr[0] = larray_assign.arr[0]+10; larray_other.arr[0] = larray_assign.arr[0] + 10;
larray_other.arr[1:3] = larray_assign.arr[1:3]; larray_other.arr[1:3] = larray_assign.arr[1:3];
if (larray_other.arr[0] != 11) $stop; if (larray_other.arr[0] != 11) $stop;
if (larray_other.arr[1] != 4) $stop; if (larray_other.arr[1] != 4) $stop;

22
test_regress/t/t_array_index_increment.v
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@ -8,18 +8,18 @@ module t;
string test_string = "abcd"; string test_string = "abcd";
// verilog_format: off
int array3d[2][3][4] = '{ int array3d[2][3][4] = '{
'{ '{'{ 0, 1, 2, 3},
'{ 0, 1, 2, 3},
'{ 4, 5, 6, 7}, '{ 4, 5, 6, 7},
'{ 8, 9, 10, 11} '{ 8, 9, 10, 11}
}, },
'{ '{'{ 12, 13, 14, 15},
'{ 12, 13, 14, 15},
'{ 16, 17, 18, 19}, '{ 16, 17, 18, 19},
'{ 20, 21, 22, 23} '{ 20, 21, 22, 23}
} }
}; };
// verilog_format: on
int pos; int pos;
int val; int val;
int i; int i;
@ -30,19 +30,19 @@ module t;
generate generate
genvar j; genvar j;
int gdata[4]; int gdata[4];
for (j=0; j < 5; j++) begin for (j = 0; j < 5; j++) begin
initial if (j >= 5) $stop; initial if (j >= 5) $stop;
end end
for (j=0; j < 5; ++j) begin for (j = 0; j < 5; ++j) begin
initial if (j >= 5) $stop; initial if (j >= 5) $stop;
end end
for (j=10; j >= 5; j--) begin for (j = 10; j >= 5; j--) begin
initial if (j < 5) $stop; initial if (j < 5) $stop;
end end
for (j=10; j >= 5; --j) begin for (j = 10; j >= 5; --j) begin
initial if (j < 5) $stop; initial if (j < 5) $stop;
end end
endgenerate endgenerate
@ -88,7 +88,7 @@ module t;
if (pos !== 1) $stop; if (pos !== 1) $stop;
if (val !== 17) $stop; if (val !== 17) $stop;
for (i=0; data[++i]<4;) begin for (i = 0; data[++i] < 4;) begin
// loop with multiple statements // loop with multiple statements
pos = i; pos = i;
val = data[i]; val = data[i];
@ -99,7 +99,9 @@ module t;
if (val !== 3) $stop; if (val !== 3) $stop;
i = 0; i = 0;
while (data[i++]<4) begin while (data[
i++
] < 4) begin
// loop with multiple statements // loop with multiple statements
pos = i; pos = i;
val = data[i]; val = data[i];

8
test_regress/t/t_array_list_bad.out
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@ -1,11 +1,11 @@
%Error: t/t_array_list_bad.v:38:25: Assignment pattern missed initializing elements: 'logic' 't3' %Error: t/t_array_list_bad.v:37:21: Assignment pattern missed initializing elements: 'logic' 't3'
: ... note: In instance 't' : ... note: In instance 't'
38 | test_out <= '{'0, '0}; 37 | test_out <= '{'0, '0};
| ^~ | ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Warning-WIDTHEXPAND: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. %Warning-WIDTHEXPAND: t/t_array_list_bad.v:37:18: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits.
: ... note: In instance 't' : ... note: In instance 't'
38 | test_out <= '{'0, '0}; 37 | test_out <= '{'0, '0};
| ^~ | ^~
... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.

9
test_regress/t/t_array_list_bad.v
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@ -12,15 +12,14 @@ package pkg;
} type_t; } type_t;
endpackage : pkg endpackage : pkg
module t module t (
(
input logic sys_clk, input logic sys_clk,
input logic sys_rst_n, input logic sys_rst_n,
input logic sys_ena, input logic sys_ena,
input pkg::type_t test_in, input pkg::type_t test_in,
output pkg::type_t test_out output pkg::type_t test_out
); );
import pkg::*; import pkg::*;
@ -29,7 +28,7 @@ module t
test_out <= '{'0, '0, '0}; test_out <= '{'0, '0, '0};
end end
else begin else begin
if(sys_ena) begin if (sys_ena) begin
test_out.t1 <= ~test_in.t1; test_out.t1 <= ~test_in.t1;
test_out.t2 <= ~test_in.t2; test_out.t2 <= ~test_in.t2;
test_out.t3 <= ~test_in.t3; test_out.t3 <= ~test_in.t3;
@ -39,4 +38,4 @@ module t
end end
end end
end end
endmodule: t endmodule : t

20
test_regress/t/t_array_mda.v
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@ -4,10 +4,10 @@
// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t ( /*AUTOARG*/
// Inputs // Inputs
clk clk
); );
input clk; input clk;
integer cyc = 0; integer cyc = 0;
@ -15,8 +15,8 @@ module t (/*AUTOARG*/
reg [63:0] sum; reg [63:0] sum;
// msg2946 // msg2946
int A [7][1], B [8][1]; int A[7][1], B[8][1];
int a [1], b [1]; int a[1], b[1];
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
a <= A[crc[2:0]]; a <= A[crc[2:0]];
b <= B[crc[2:0]]; b <= B[crc[2:0]];
@ -24,14 +24,14 @@ module t (/*AUTOARG*/
wire [63:0] result = {a[0], b[0]}; wire [63:0] result = {a[0], b[0]};
// Test loop // Test loop
always @ (posedge clk) begin always @(posedge clk) begin
`ifdef TEST_VERBOSE `ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif `endif
cyc <= cyc + 1; cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin if (cyc == 0) begin
// Setup // Setup
crc <= 64'h5aef0c8d_d70a4497; crc <= 64'h5aef0c8d_d70a4497;
sum <= '0; sum <= '0;
@ -51,16 +51,16 @@ module t (/*AUTOARG*/
B[6][0] <= 32'h2_6; B[6][0] <= 32'h2_6;
B[7][0] <= 32'h2_7; B[7][0] <= 32'h2_7;
end end
else if (cyc<10) begin else if (cyc < 10) begin
sum <= '0; sum <= '0;
end end
else if (cyc<90) begin else if (cyc < 90) begin
end end
else if (cyc==99) begin else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop; if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match) // What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h619f75c3a6d948bd `define EXPECTED_SUM 64'h619f75c3a6d948bd
if (sum !== `EXPECTED_SUM) $stop; if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;

2
test_regress/t/t_array_method_bad.out
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@ -1,4 +1,4 @@
%Error: t/t_array_method_bad.v:11:9: Unknown built-in array method 'mex' %Error: t/t_array_method_bad.v:11:7: Unknown built-in array method 'mex'
: ... note: In instance 't' : ... note: In instance 't'
11 | q.mex; 11 | q.mex;
| ^~~ | ^~~

4
test_regress/t/t_array_method_map.out
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@ -1,9 +1,9 @@
%Error-UNSUPPORTED: t/t_array_method_map.v:19:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5) %Error-UNSUPPORTED: t/t_array_method_map.v:19:13: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5)
: ... note: In instance 't' : ... note: In instance 't'
19 | res = a.map(el) with (el == 200); 19 | res = a.map(el) with (el == 200);
| ^~~ | ^~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: t/t_array_method_map.v:19:15: Unknown built-in array method 'map' %Error: t/t_array_method_map.v:19:13: Unknown built-in array method 'map'
: ... note: In instance 't' : ... note: In instance 't'
19 | res = a.map(el) with (el == 200); 19 | res = a.map(el) with (el == 200);
| ^~~ | ^~~

17
test_regress/t/t_array_non_blocking_loop.v
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@ -5,12 +5,12 @@
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
interface intf interface intf #(
#( parameter int WRITE_DATA_WIDTH
parameter int WRITE_DATA_WIDTH) (); ) ();
logic [WRITE_DATA_WIDTH-1:0] writedata; logic [WRITE_DATA_WIDTH-1:0] writedata;
endinterface endinterface
module t( /*AUTOARG*/ module t ( /*AUTOARG*/
clk clk
); );
@ -19,19 +19,16 @@ module t( /*AUTOARG*/
genvar num_chunks; genvar num_chunks;
for (num_chunks = 1; num_chunks <= 2; num_chunks++) begin : gen_n for (num_chunks = 1; num_chunks <= 2; num_chunks++) begin : gen_n
localparam int decoded_width = 55 * num_chunks; localparam int decoded_width = 55 * num_chunks;
intf #( intf #(.WRITE_DATA_WIDTH(decoded_width)) the_intf ();
.WRITE_DATA_WIDTH(decoded_width))
the_intf ();
always @(posedge clk) begin always @(posedge clk) begin
for (int i = 0; i < decoded_width; i++) for (int i = 0; i < decoded_width; i++) the_intf.writedata[i] <= '1;
the_intf.writedata[i] <= '1;
$display("%0d", the_intf.writedata); $display("%0d", the_intf.writedata);
end end
end end
endgenerate endgenerate
// finish report // finish report
always @ (posedge clk) begin always @(posedge clk) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end

6
test_regress/t/t_array_packed_endian.v
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@ -4,12 +4,12 @@
// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-FileCopyrightText: 2020 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
// verilog_format: off
typedef struct packed { typedef struct packed {logic [7:0] a;} tb_t;
logic [7:0] a;
} tb_t;
typedef struct packed { typedef struct packed {
// verilator lint_off ASCRANGE // verilator lint_off ASCRANGE

2
test_regress/t/t_array_packed_sign.v
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@ -46,7 +46,7 @@ module t;
end end
if ($signed((unnamed >>> 1) >> 11) != 1) begin if ($signed((unnamed >>> 1) >> 11) != 1) begin
$stop;// $stop; //
end end
if ($signed((unnamed[1] >>> 1) >> 5) != 0) begin if ($signed((unnamed[1] >>> 1) >> 5) != 0) begin
$stop; $stop;

9
test_regress/t/t_array_packed_sysfunct.v
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@ -4,16 +4,15 @@
// SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-FileCopyrightText: 2009 Iztok Jeras
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk
); );
input clk;
// parameters for array sizes // parameters for array sizes
localparam WA = 4; localparam WA = 4;
localparam WB = 6; localparam WB = 6;

196
test_regress/t/t_array_packed_write_read.v
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@ -4,12 +4,9 @@
// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-FileCopyrightText: 2012 Iztok Jeras
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
// parameters for array sizes // parameters for array sizes
localparam WA = 8; // address dimension size localparam WA = 8; // address dimension size
@ -18,9 +15,9 @@ module t (/*AUTOARG*/
localparam NO = 10; // number of access events localparam NO = 10; // number of access events
// 2D packed arrays // 2D packed arrays
logic [WA-1:0] [WB-1:0] array_dsc; // descending range array logic [WA-1:0][WB-1:0] array_dsc; // descending range array
/* verilator lint_off ASCRANGE */ /* verilator lint_off ASCRANGE */
logic [0:WA-1] [0:WB-1] array_asc; // ascending range array logic [0:WA-1][0:WB-1] array_asc; // ascending range array
/* verilator lint_on ASCRANGE */ /* verilator lint_on ASCRANGE */
integer cnt = 0; integer cnt = 0;
@ -30,119 +27,120 @@ module t (/*AUTOARG*/
initial packedArray = '0; initial packedArray = '0;
// event counter // event counter
always @ (posedge clk) begin always @(posedge clk) begin
cnt <= cnt + 1; cnt <= cnt + 1;
end end
// finish report // finish report
always @ (posedge clk) always @(posedge clk)
if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin if ((cnt[30:2] == NO) && (cnt[1:0] == 2'd0)) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
// descending range // descending range
// verilog_format: off
always @ (posedge clk) always @ (posedge clk)
if (cnt[1:0]==2'd0) begin if (cnt[1:0] == 2'd0) begin
// initialize to defaaults (all bits to 0) // initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) array_dsc <= '0; if (cnt[30:2] == 0) array_dsc <= '0;
else if (cnt[30:2]==1) array_dsc <= '0; else if (cnt[30:2] == 1) array_dsc <= '0;
else if (cnt[30:2]==2) array_dsc <= '0; else if (cnt[30:2] == 2) array_dsc <= '0;
else if (cnt[30:2]==3) array_dsc <= '0; else if (cnt[30:2] == 3) array_dsc <= '0;
else if (cnt[30:2]==4) array_dsc <= '0; else if (cnt[30:2] == 4) array_dsc <= '0;
else if (cnt[30:2]==5) array_dsc <= '0; else if (cnt[30:2] == 5) array_dsc <= '0;
else if (cnt[30:2]==6) array_dsc <= '0; else if (cnt[30:2] == 6) array_dsc <= '0;
else if (cnt[30:2]==7) array_dsc <= '0; else if (cnt[30:2] == 7) array_dsc <= '0;
else if (cnt[30:2]==8) array_dsc <= '0; else if (cnt[30:2] == 8) array_dsc <= '0;
else if (cnt[30:2]==9) array_dsc <= '0; else if (cnt[30:2] == 9) array_dsc <= '0;
end else if (cnt[1:0]==2'd1) begin end else if (cnt[1:0] == 2'd1) begin
// write value to array // write value to array
if (cnt[30:2]==0) begin end if (cnt[30:2] == 0) begin end
else if (cnt[30:2]==1) array_dsc <= {WA *WB +0{1'b1}}; else if (cnt[30:2] == 1) array_dsc <= {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2] == 2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2] == 3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2] == 4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2] == 5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2] == 6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2] == 7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; else if (cnt[30:2] == 8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; else if (cnt[30:2] == 9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin end else if (cnt[1:0] == 2'd2) begin
// check array value // check array value
if (cnt[30:2]==0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end if (cnt[30:2] == 0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2] == 1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2] == 2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2] == 3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2] == 4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2] == 5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2] == 6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2] == 7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2] == 8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end
else if (cnt[30:2]==9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2] == 9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end
end else if (cnt[1:0]==2'd3) begin end else if (cnt[1:0] == 2'd3) begin
// read value from array (not a very good test for now) // read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end if (cnt[30:2] == 0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end else if (cnt[30:2] == 1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2] == 2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2] == 3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2] == 4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2] == 5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2] == 6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2] == 7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end else if (cnt[30:2] == 8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end else if (cnt[30:2] == 9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end
end end
// ascending range // ascending range
always @ (posedge clk) always @ (posedge clk)
if (cnt[1:0]==2'd0) begin if (cnt[1:0] == 2'd0) begin
// initialize to defaaults (all bits to 0) // initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) array_asc <= '0; if (cnt[30:2] == 0) array_asc <= '0;
else if (cnt[30:2]==1) array_asc <= '0; else if (cnt[30:2] == 1) array_asc <= '0;
else if (cnt[30:2]==2) array_asc <= '0; else if (cnt[30:2] == 2) array_asc <= '0;
else if (cnt[30:2]==3) array_asc <= '0; else if (cnt[30:2] == 3) array_asc <= '0;
else if (cnt[30:2]==4) array_asc <= '0; else if (cnt[30:2] == 4) array_asc <= '0;
else if (cnt[30:2]==5) array_asc <= '0; else if (cnt[30:2] == 5) array_asc <= '0;
else if (cnt[30:2]==6) array_asc <= '0; else if (cnt[30:2] == 6) array_asc <= '0;
else if (cnt[30:2]==7) array_asc <= '0; else if (cnt[30:2] == 7) array_asc <= '0;
else if (cnt[30:2]==8) array_asc <= '0; else if (cnt[30:2] == 8) array_asc <= '0;
else if (cnt[30:2]==9) array_asc <= '0; else if (cnt[30:2] == 9) array_asc <= '0;
end else if (cnt[1:0]==2'd1) begin end else if (cnt[1:0] == 2'd1) begin
// write value to array // write value to array
if (cnt[30:2]==0) begin end if (cnt[30:2] == 0) begin end
else if (cnt[30:2]==1) array_asc <= {WA *WB +0{1'b1}}; else if (cnt[30:2] == 1) array_asc <= {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2] == 2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2] == 3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_asc [0 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2] == 4) array_asc [0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_asc [ WA -1] <= {1 *WB +0{1'b1}}; else if (cnt[30:2] == 5) array_asc [ WA -1] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2] == 6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2] == 7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}}; else if (cnt[30:2] == 8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; else if (cnt[30:2] == 9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin end else if (cnt[1:0] == 2'd2) begin
// check array value // check array value
if (cnt[30:2]==0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end if (cnt[30:2] == 0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2] == 1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2] == 2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2] == 3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2] == 4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2] == 5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2] == 6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2] == 7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2] == 8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end
else if (cnt[30:2]==9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2] == 9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end
end else if (cnt[1:0]==2'd3) begin end else if (cnt[1:0] == 2'd3) begin
// read value from array (not a very good test for now) // read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end if (cnt[30:2] == 0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end else if (cnt[30:2] == 1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2] == 2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2] == 3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2] == 4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2] == 5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2] == 6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2] == 7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end else if (cnt[30:2] == 8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end else if (cnt[30:2] == 9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end
end end
endmodule endmodule

14
test_regress/t/t_array_pattern_2d.v
View File

@ -7,19 +7,19 @@
//bug991 //bug991
module t; module t;
logic [31:0] array_assign [3:0]; logic [31:0] array_assign[3:0];
logic [31:0] array_other [3:0]; logic [31:0] array_other[3:0];
logic [31:0] larray_assign [0:3]; logic [31:0] larray_assign[0:3];
logic [31:0] larray_other [0:3]; logic [31:0] larray_other[0:3];
logic [31:0] array_neg [-1:1]; logic [31:0] array_neg[-1:1];
initial begin initial begin
array_assign[0] = 32'd1; array_assign[0] = 32'd1;
array_assign[3:1] = '{32'd4, 32'd3, 32'd2}; array_assign[3:1] = '{32'd4, 32'd3, 32'd2};
array_other[0] = array_assign[0]+10; array_other[0] = array_assign[0] + 10;
array_other[3:1] = array_assign[3:1]; array_other[3:1] = array_assign[3:1];
if (array_other[0] != 11) $stop; if (array_other[0] != 11) $stop;
if (array_other[1] != 2) $stop; if (array_other[1] != 2) $stop;
@ -29,7 +29,7 @@ module t;
larray_assign[0] = 32'd1; larray_assign[0] = 32'd1;
larray_assign[1:3] = '{32'd4, 32'd3, 32'd2}; larray_assign[1:3] = '{32'd4, 32'd3, 32'd2};
larray_other[0] = larray_assign[0]+10; larray_other[0] = larray_assign[0] + 10;
larray_other[1:3] = larray_assign[1:3]; larray_other[1:3] = larray_assign[1:3];
if (larray_other[0] != 11) $stop; if (larray_other[0] != 11) $stop;
if (larray_other[1] != 4) $stop; if (larray_other[1] != 4) $stop;

4
test_regress/t/t_array_pattern_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_array_pattern_bad.v:24:18: Assignment pattern key 'valids' not found as member %Error: t/t_array_pattern_bad.v:21:39: Assignment pattern key 'valids' not found as member
: ... note: In instance 't' : ... note: In instance 't'
24 | valids: '1}; 21 | always_comb myinfo = '{default: '0, valids: '1};
| ^~~~~~ | ^~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to %Error: Exiting due to

15
test_regress/t/t_array_pattern_bad.v
View File

@ -6,21 +6,18 @@
// bug1364 // bug1364
module t (/*AUTOARG*/ module t ( /*AUTOARG*/
// Inputs // Inputs
clk, res clk,
); res
);
input clk; input clk;
input res; input res;
typedef struct packed { typedef struct packed {logic [3:0] port_num;} info_t;
logic [3:0] port_num;
} info_t;
info_t myinfo; info_t myinfo;
always_comb always_comb myinfo = '{default: '0, valids: '1};
myinfo = '{default: '0,
valids: '1};
endmodule endmodule

4
test_regress/t/t_array_pattern_bad2.out
View File

@ -1,6 +1,6 @@
%Error: t/t_array_pattern_bad2.v:22:16: Multiple '{ default: } clauses %Error: t/t_array_pattern_bad2.v:20:24: Multiple '{ default: } clauses
: ... note: In instance 't' : ... note: In instance 't'
22 | myinfo = '{default: '0, 20 | always_comb myinfo = '{default: '0, default: '1};
| ^~ | ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to %Error: Exiting due to

15
test_regress/t/t_array_pattern_bad2.v
View File

@ -6,20 +6,17 @@
// bug1364 // bug1364
module t (/*AUTOARG*/ module t ( /*AUTOARG*/
// Inputs // Inputs
clk, res clk,
); res
);
input clk; input clk;
input res; input res;
typedef struct packed { typedef struct packed {logic [3:0] port_num;} info_t;
logic [3:0] port_num;
} info_t;
info_t myinfo; info_t myinfo;
always_comb always_comb myinfo = '{default: '0, default: '1}; // Bad
myinfo = '{default: '0,
default: '1}; // Bad
endmodule endmodule

8
test_regress/t/t_array_pattern_bad3.out
View File

@ -1,13 +1,13 @@
%Error: t/t_array_pattern_bad3.v:20:15: Assignment pattern key used multiple times: 1 %Error: t/t_array_pattern_bad3.v:19:9: Assignment pattern key used multiple times: 1
: ... note: In instance 't' : ... note: In instance 't'
20 | 1: '1}; 19 | 1: '1
| ^ | ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_array_pattern_bad3.v:21:13: Assignment pattern with too many elements %Error: t/t_array_pattern_bad3.v:21:11: Assignment pattern with too many elements
: ... note: In instance 't' : ... note: In instance 't'
21 | arr = '{'0, '1, '0, '1}; 21 | arr = '{'0, '1, '0, '1};
| ^~ | ^~
%Error: t/t_array_pattern_bad3.v:22:13: Assignment pattern missed initializing elements: 2 %Error: t/t_array_pattern_bad3.v:22:11: Assignment pattern missed initializing elements: 2
: ... note: In instance 't' : ... note: In instance 't'
22 | arr = '{'0, '1}; 22 | arr = '{'0, '1};
| ^~ | ^~

18
test_regress/t/t_array_pattern_bad3.v
View File

@ -6,18 +6,18 @@
// bug1364 // bug1364
module t (/*AUTOARG*/ module t (
// Inputs input clk,
clk, res input res
); );
input clk;
input res;
int arr[3]; int arr[3];
initial begin initial begin
arr = '{default: '0, arr = '{
1: '0, default: '0, //
1: '1}; // Bad 1: '0, //
1: '1
}; // Bad
arr = '{'0, '1, '0, '1}; // Bad, too many arr = '{'0, '1, '0, '1}; // Bad, too many
arr = '{'0, '1}; // Bad, too few arr = '{'0, '1}; // Bad, too few
end end

16
test_regress/t/t_array_pattern_enum.v
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@ -6,25 +6,21 @@
package Pkg; package Pkg;
typedef enum { typedef enum {
RED=0, RED = 0,
GREEN=1, GREEN = 1,
BLUE=2 BLUE = 2
} color_t; } color_t;
typedef struct { typedef struct {color_t pixels[32];} line_t;
color_t pixels[32];
} line_t;
typedef struct { typedef struct {line_t line[32];} screen_t;
line_t line[32];
} screen_t;
endpackage endpackage
module t; module t;
Pkg::screen_t screen; Pkg::screen_t screen;
initial begin initial begin
screen = '{ default: '0, Pkg::color_t: Pkg::RED}; screen = '{default: '0, Pkg::color_t: Pkg::RED};
$display("%p", screen); $display("%p", screen);
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;

12
test_regress/t/t_array_pattern_packed.v
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@ -4,17 +4,15 @@
// SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-FileCopyrightText: 2009 Iztok Jeras
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk; logic [1:0][3:0][3:0] array_simp; // descending range array
logic [1:0] [3:0] [3:0] array_simp; // descending range array
logic [3:0] array_oned; logic [3:0] array_oned;
// verilog_format: off
initial begin initial begin
array_oned = '{2:1'b1, 0:1'b1, default:1'b0}; array_oned = '{2:1'b1, 0:1'b1, default:1'b0};
if (array_oned != 4'b0101) $stop; if (array_oned != 4'b0101) $stop;

38
test_regress/t/t_array_query.v
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@ -7,39 +7,35 @@
// SPDX-FileCopyrightText: 2012 Jeremy Bennett, Embecosm // SPDX-FileCopyrightText: 2012 Jeremy Bennett, Embecosm
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
wire a = clk; wire a = clk;
wire b = 1'b0; wire b = 1'b0;
reg c; reg c;
array_test array_test_i (/*AUTOINST*/ array_test array_test_i ( /*AUTOINST*/
// Inputs // Inputs
.clk (clk)); .clk(clk)
);
endmodule endmodule
// Check the array sizing functions work correctly. // Check the array sizing functions work correctly.
module array_test module array_test #(
parameter LEFT = 5,
#( parameter RIGHT = 55
LEFT = 5, ) ( /*AUTOARG*/
RIGHT = 55)
(/*AUTOARG*/
// Inputs // Inputs
clk clk
); );
input clk; input clk;
// verilator lint_off ASCRANGE // verilator lint_off ASCRANGE
reg [7:0] a [LEFT:RIGHT]; reg [7:0] a[LEFT:RIGHT];
// verilator lint_on ASCRANGE // verilator lint_on ASCRANGE
typedef reg [7:0] r_t; typedef reg [7:0] r_t;
@ -49,16 +45,16 @@ module array_test
integer s; integer s;
always @(posedge clk) begin always @(posedge clk) begin
l = $left (a); l = $left(a);
r = $right (a); r = $right(a);
s = $size (a); s = $size(a);
`ifdef TEST_VERBOSE `ifdef TEST_VERBOSE
$write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s); $write("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s);
`endif `endif
if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop; if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop;
if ($left(r_t)!=7 || $right(r_t)!=0 || $size(r_t)!=8 || $bits(r_t) !=8) $stop; if ($left(r_t) != 7 || $right(r_t) != 0 || $size(r_t) != 8 || $bits(r_t) != 8) $stop;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end

4
test_regress/t/t_array_query_with.v
View File

@ -20,8 +20,8 @@ class Cls;
endfunction endfunction
endclass endclass
module t (/*AUTOARG*/ module t ( /*AUTOARG*/
); );
function bit test_find; function bit test_find;
string bar[$]; string bar[$];

24
test_regress/t/t_array_rev.v
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@ -4,27 +4,24 @@
// SPDX-FileCopyrightText: 2016 Geoff Barrett // SPDX-FileCopyrightText: 2016 Geoff Barrett
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
integer cyc = 0; integer cyc = 0;
// verilator lint_off ASCRANGE // verilator lint_off ASCRANGE
logic arrd [0:1] = '{ 1'b1, 1'b0 }; logic arrd[0:1] = '{1'b1, 1'b0};
// verilator lint_on ASCRANGE // verilator lint_on ASCRANGE
logic y0, y1; logic y0, y1;
logic localbkw [1:0]; logic localbkw[1:0];
arr_rev arr_rev_u ( arr_rev arr_rev_u (
.arrbkw (arrd), .arrbkw(arrd),
.y0(y0), .y0(y0),
.y1(y1) .y1(y1)
); );
always @ (posedge clk) begin always @(posedge clk) begin
if (arrd[0] != 1'b1) $stop; if (arrd[0] != 1'b1) $stop;
if (arrd[1] != 1'b0) $stop; if (arrd[1] != 1'b0) $stop;
@ -48,12 +45,11 @@ module t (/*AUTOARG*/
endmodule endmodule
module arr_rev module arr_rev (
( input var logic arrbkw[1:0],
input var logic arrbkw [1:0],
output var logic y0, output var logic y0,
output var logic y1 output var logic y1
); );
always_comb y0 = arrbkw[0]; always_comb y0 = arrbkw[0];
always_comb y1 = arrbkw[1]; always_comb y1 = arrbkw[1];

6
test_regress/t/t_array_type_methods.v
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@ -4,14 +4,16 @@
// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-FileCopyrightText: 2014 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t; module t;
logic [3:0] foo [1:0]; logic [3:0] foo[1:0];
logic [3:0] fooe [1:0]; logic [3:0] fooe[1:0];
initial begin initial begin
foo[0] = 4'b0101; foo[0] = 4'b0101;
foo[1] = 4'b0011; foo[1] = 4'b0011;

10
test_regress/t/t_array_unpacked_public.v
View File

@ -4,10 +4,10 @@
// SPDX-FileCopyrightText: 2020 Stefan Wallentowitz // SPDX-FileCopyrightText: 2020 Stefan Wallentowitz
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t(); module t;
logic din [0:15]; logic din[0:15];
array_test array_test_inst(.din(din)); array_test array_test_inst (.din(din));
initial begin initial begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
@ -15,7 +15,7 @@ module t();
end end
endmodule endmodule
module array_test( module array_test (
input din [0:15] input din[0:15]
); );
endmodule endmodule

16
test_regress/t/t_assert_always_unsup.out
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@ -1,15 +1,15 @@
%Error-UNSUPPORTED: t/t_assert_always_unsup.v:21:7: Unsupported: always[] (in property expression) %Error-UNSUPPORTED: t/t_assert_always_unsup.v:20:5: Unsupported: always[] (in property expression)
21 | always [2:5] a; 20 | always [2:5] a;
| ^~~~~~ | ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_assert_always_unsup.v:25:7: Unsupported: s_always (in property expression) %Error-UNSUPPORTED: t/t_assert_always_unsup.v:24:5: Unsupported: s_always (in property expression)
25 | s_always [2:5] a; 24 | s_always [2:5] a;
| ^~~~~~~~ | ^~~~~~~~
%Error-UNSUPPORTED: t/t_assert_always_unsup.v:29:7: Unsupported: eventually[] (in property expression) %Error-UNSUPPORTED: t/t_assert_always_unsup.v:28:5: Unsupported: eventually[] (in property expression)
29 | eventually [2:5] a; 28 | eventually [2:5] a;
| ^~~~~~~~~~ | ^~~~~~~~~~
%Error: t/t_assert_always_unsup.v:33:20: syntax error, unexpected ']', expecting ':' %Error: t/t_assert_always_unsup.v:32:18: syntax error, unexpected ']', expecting ':'
33 | eventually [2] a; 32 | eventually [2] a;
| ^ | ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Cannot continue %Error: Cannot continue

7
test_regress/t/t_assert_always_unsup.v
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@ -4,11 +4,10 @@
// SPDX-FileCopyrightText: 2022-2025 Antmicro // SPDX-FileCopyrightText: 2022-2025 Antmicro
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
clk input clk
); );
input clk;
int cyc = 0; int cyc = 0;
logic val = 0; logic val = 0;

62
test_regress/t/t_assert_basic.v
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@ -4,46 +4,58 @@
// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-FileCopyrightText: 2007 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
reg toggle; reg toggle;
integer cyc; initial cyc=1; integer cyc;
initial cyc = 1;
wire [7:0] cyc_copy = cyc[7:0]; wire [7:0] cyc_copy = cyc[7:0];
always @ (negedge clk) begin always @(negedge clk) begin
AssertionFalse1: assert (cyc<100); AssertionFalse1 : assert (cyc < 100);
assert (!(cyc==5) || toggle); assert (!(cyc == 5) || toggle);
// FIX cover {cyc==3 || cyc==4}; // FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1"; // FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1"; // FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end end
always @ (posedge clk) begin always @(posedge clk) begin
if (cyc!=0) begin if (cyc != 0) begin
cyc <= cyc + 1; cyc <= cyc + 1;
toggle <= !cyc[0]; toggle <= !cyc[0];
if (cyc==7) assert (cyc[0] == cyc[1]); // bug743 if (cyc == 7) assert (cyc[0] == cyc[1]); // bug743
if (cyc==9) begin if (cyc == 9) begin
`ifdef FAILING_ASSERTIONS `ifdef FAILING_ASSERTIONS
assert (0) else $info; assert (0)
assert (0) else $info("Info message"); else $info;
assume (0) else $info("Info message from failing assumption"); assert (0)
assert (0) else $info("Info message, cyc=%d", cyc); else $info("Info message");
InWarningBlock: assert (0) else $warning; assume (0)
InWarningMBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); else $info("Info message from failing assumption");
InErrorBlock: assert (0) else $error; assert (0)
InErrorMBlock: assert (0) else $error("Error...."); else $info("Info message, cyc=%d", cyc);
assert (0) else $fatal(1, "Fatal...."); InWarningBlock :
assert (0) else $fatal; assert (0)
else $warning;
InWarningMBlock :
assert (0)
else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
InErrorBlock :
assert (0)
else $error;
InErrorMBlock :
assert (0)
else $error("Error....");
assert (0)
else $fatal(1, "Fatal....");
assert (0)
else $fatal;
`endif `endif
end end
if (cyc==10) begin if (cyc == 10) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end

12
test_regress/t/t_assert_casez.v
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@ -11,15 +11,15 @@ module t;
initial begin initial begin
value = 2'b00; value = 2'b00;
unique casez (value) unique casez (value)
2'b00 : ; 2'b00: ;
2'b01 : ; 2'b01: ;
2'b1? : ; 2'b1?: ;
endcase endcase
value = 2'b11; value = 2'b11;
unique casez (value) unique casez (value)
2'b00 : ; 2'b00: ;
2'b01 : ; 2'b01: ;
2'b1? : ; 2'b1?: ;
endcase endcase
unique casez (1'b1) unique casez (1'b1)
default: ; default: ;

4
test_regress/t/t_assert_clock_event_unsup.out
View File

@ -1,5 +1,5 @@
%Error-UNSUPPORTED: t/t_assert_clock_event_unsup.v:26:7: Unsupported: Clock event before property call and in its body %Error-UNSUPPORTED: t/t_assert_clock_event_unsup.v:24:5: Unsupported: Clock event before property call and in its body
26 | @(negedge clk) 24 | @(negedge clk) check(
| ^ | ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to %Error: Exiting due to

17
test_regress/t/t_assert_clock_event_unsup.v
View File

@ -4,11 +4,10 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
clk input clk
); );
input clk;
int cyc = 0; int cyc = 0;
logic val = 0; logic val = 0;
@ -18,16 +17,16 @@ module t (/*AUTOARG*/
end end
property check(int cyc_mod_2, logic expected); property check(int cyc_mod_2, logic expected);
@(posedge clk) @(posedge clk) cyc % 2 == cyc_mod_2 |=> val == expected;
cyc % 2 == cyc_mod_2 |=> val == expected;
endproperty endproperty
property check_if_1(int cyc_mod_2); property check_if_1(int cyc_mod_2);
@(negedge clk) @(negedge clk) check(
check(cyc_mod_2, 1); cyc_mod_2, 1
);
endproperty endproperty
assert property(check_if_1(1)) assert property (check_if_1(1))
else begin else begin
// Assertion should fail // Assertion should fail
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");

8
test_regress/t/t_assert_cover.v
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@ -4,12 +4,10 @@
// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-FileCopyrightText: 2007 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
reg toggle; reg toggle;
integer cyc; initial cyc=1; integer cyc; initial cyc=1;

304
test_regress/t/t_assert_ctl_arg.dat.out
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@ -1,153 +1,153 @@
# SystemC::Coverage-3 # SystemC::Coverage-3
C 'ft/t_assert_ctl_arg.vl100n32tuserpagev_user/tocover_simple_immediate_100htop.t.cover_simple_immediate_100' 1 C 'ft/t_assert_ctl_arg.vl102n31tuserpagev_user/tocover_simple_immediate_102htop.t.cover_simple_immediate_102' 0
C 'ft/t_assert_ctl_arg.vl100n37tuserpagev_user/tocover_simple_immediate_stmt_100htop.t.cover_simple_immediate_stmt_100' 1 C 'ft/t_assert_ctl_arg.vl102n36tuserpagev_user/tocover_simple_immediate_stmt_102htop.t.cover_simple_immediate_stmt_102' 0
C 'ft/t_assert_ctl_arg.vl100n40tuserpagev_user/tocover_final_deferred_immediate_100htop.t.cover_final_deferred_immediate_100' 1 C 'ft/t_assert_ctl_arg.vl102n39tuserpagev_user/tocover_final_deferred_immediate_102htop.t.cover_final_deferred_immediate_102' 0
C 'ft/t_assert_ctl_arg.vl100n43tuserpagev_user/tocover_observed_deferred_immediate_100htop.t.cover_observed_deferred_immediate_100' 1 C 'ft/t_assert_ctl_arg.vl102n42tuserpagev_user/tocover_observed_deferred_immediate_102htop.t.cover_observed_deferred_immediate_102' 0
C 'ft/t_assert_ctl_arg.vl100n45tuserpagev_user/tocover_final_deferred_immediate_stmt_100htop.t.cover_final_deferred_immediate_stmt_100' 1 C 'ft/t_assert_ctl_arg.vl102n44tuserpagev_user/tocover_final_deferred_immediate_stmt_102htop.t.cover_final_deferred_immediate_stmt_102' 0
C 'ft/t_assert_ctl_arg.vl100n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_100htop.t.cover_observed_deferred_immediate_stmt_100' 1 C 'ft/t_assert_ctl_arg.vl102n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_102htop.t.cover_observed_deferred_immediate_stmt_102' 0
C 'ft/t_assert_ctl_arg.vl103n32tuserpagev_user/tocover_simple_immediate_103htop.t.cover_simple_immediate_103' 0 C 'ft/t_assert_ctl_arg.vl105n31tuserpagev_user/tocover_simple_immediate_105htop.t.cover_simple_immediate_105' 1
C 'ft/t_assert_ctl_arg.vl103n37tuserpagev_user/tocover_simple_immediate_stmt_103htop.t.cover_simple_immediate_stmt_103' 0 C 'ft/t_assert_ctl_arg.vl105n36tuserpagev_user/tocover_simple_immediate_stmt_105htop.t.cover_simple_immediate_stmt_105' 1
C 'ft/t_assert_ctl_arg.vl103n40tuserpagev_user/tocover_final_deferred_immediate_103htop.t.cover_final_deferred_immediate_103' 0 C 'ft/t_assert_ctl_arg.vl105n39tuserpagev_user/tocover_final_deferred_immediate_105htop.t.cover_final_deferred_immediate_105' 1
C 'ft/t_assert_ctl_arg.vl103n43tuserpagev_user/tocover_observed_deferred_immediate_103htop.t.cover_observed_deferred_immediate_103' 0 C 'ft/t_assert_ctl_arg.vl105n42tuserpagev_user/tocover_observed_deferred_immediate_105htop.t.cover_observed_deferred_immediate_105' 1
C 'ft/t_assert_ctl_arg.vl103n45tuserpagev_user/tocover_final_deferred_immediate_stmt_103htop.t.cover_final_deferred_immediate_stmt_103' 0 C 'ft/t_assert_ctl_arg.vl105n44tuserpagev_user/tocover_final_deferred_immediate_stmt_105htop.t.cover_final_deferred_immediate_stmt_105' 1
C 'ft/t_assert_ctl_arg.vl103n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_103htop.t.cover_observed_deferred_immediate_stmt_103' 0 C 'ft/t_assert_ctl_arg.vl105n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_105htop.t.cover_observed_deferred_immediate_stmt_105' 1
C 'ft/t_assert_ctl_arg.vl106n32tuserpagev_user/tocover_simple_immediate_106htop.t.cover_simple_immediate_106' 1 C 'ft/t_assert_ctl_arg.vl107n31tuserpagev_user/tocover_simple_immediate_107htop.t.cover_simple_immediate_107' 1
C 'ft/t_assert_ctl_arg.vl106n37tuserpagev_user/tocover_simple_immediate_stmt_106htop.t.cover_simple_immediate_stmt_106' 1 C 'ft/t_assert_ctl_arg.vl107n36tuserpagev_user/tocover_simple_immediate_stmt_107htop.t.cover_simple_immediate_stmt_107' 1
C 'ft/t_assert_ctl_arg.vl106n40tuserpagev_user/tocover_final_deferred_immediate_106htop.t.cover_final_deferred_immediate_106' 1 C 'ft/t_assert_ctl_arg.vl107n39tuserpagev_user/tocover_final_deferred_immediate_107htop.t.cover_final_deferred_immediate_107' 1
C 'ft/t_assert_ctl_arg.vl106n43tuserpagev_user/tocover_observed_deferred_immediate_106htop.t.cover_observed_deferred_immediate_106' 1 C 'ft/t_assert_ctl_arg.vl107n42tuserpagev_user/tocover_observed_deferred_immediate_107htop.t.cover_observed_deferred_immediate_107' 1
C 'ft/t_assert_ctl_arg.vl106n45tuserpagev_user/tocover_final_deferred_immediate_stmt_106htop.t.cover_final_deferred_immediate_stmt_106' 1 C 'ft/t_assert_ctl_arg.vl107n44tuserpagev_user/tocover_final_deferred_immediate_stmt_107htop.t.cover_final_deferred_immediate_stmt_107' 1
C 'ft/t_assert_ctl_arg.vl106n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_106htop.t.cover_observed_deferred_immediate_stmt_106' 1 C 'ft/t_assert_ctl_arg.vl107n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_107htop.t.cover_observed_deferred_immediate_stmt_107' 1
C 'ft/t_assert_ctl_arg.vl108n32tuserpagev_user/tocover_simple_immediate_108htop.t.cover_simple_immediate_108' 1 C 'ft/t_assert_ctl_arg.vl109n31tuserpagev_user/tocover_simple_immediate_109htop.t.cover_simple_immediate_109' 0
C 'ft/t_assert_ctl_arg.vl108n37tuserpagev_user/tocover_simple_immediate_stmt_108htop.t.cover_simple_immediate_stmt_108' 1 C 'ft/t_assert_ctl_arg.vl109n36tuserpagev_user/tocover_simple_immediate_stmt_109htop.t.cover_simple_immediate_stmt_109' 0
C 'ft/t_assert_ctl_arg.vl108n40tuserpagev_user/tocover_final_deferred_immediate_108htop.t.cover_final_deferred_immediate_108' 1 C 'ft/t_assert_ctl_arg.vl109n39tuserpagev_user/tocover_final_deferred_immediate_109htop.t.cover_final_deferred_immediate_109' 0
C 'ft/t_assert_ctl_arg.vl108n43tuserpagev_user/tocover_observed_deferred_immediate_108htop.t.cover_observed_deferred_immediate_108' 1 C 'ft/t_assert_ctl_arg.vl109n42tuserpagev_user/tocover_observed_deferred_immediate_109htop.t.cover_observed_deferred_immediate_109' 0
C 'ft/t_assert_ctl_arg.vl108n45tuserpagev_user/tocover_final_deferred_immediate_stmt_108htop.t.cover_final_deferred_immediate_stmt_108' 1 C 'ft/t_assert_ctl_arg.vl109n44tuserpagev_user/tocover_final_deferred_immediate_stmt_109htop.t.cover_final_deferred_immediate_stmt_109' 0
C 'ft/t_assert_ctl_arg.vl108n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_108htop.t.cover_observed_deferred_immediate_stmt_108' 1 C 'ft/t_assert_ctl_arg.vl109n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_109htop.t.cover_observed_deferred_immediate_stmt_109' 0
C 'ft/t_assert_ctl_arg.vl110n32tuserpagev_user/tocover_simple_immediate_110htop.t.cover_simple_immediate_110' 0 C 'ft/t_assert_ctl_arg.vl111n31tuserpagev_user/tocover_simple_immediate_111htop.t.cover_simple_immediate_111' 1
C 'ft/t_assert_ctl_arg.vl110n37tuserpagev_user/tocover_simple_immediate_stmt_110htop.t.cover_simple_immediate_stmt_110' 0 C 'ft/t_assert_ctl_arg.vl111n36tuserpagev_user/tocover_simple_immediate_stmt_111htop.t.cover_simple_immediate_stmt_111' 1
C 'ft/t_assert_ctl_arg.vl110n40tuserpagev_user/tocover_final_deferred_immediate_110htop.t.cover_final_deferred_immediate_110' 0 C 'ft/t_assert_ctl_arg.vl111n39tuserpagev_user/tocover_final_deferred_immediate_111htop.t.cover_final_deferred_immediate_111' 1
C 'ft/t_assert_ctl_arg.vl110n43tuserpagev_user/tocover_observed_deferred_immediate_110htop.t.cover_observed_deferred_immediate_110' 0 C 'ft/t_assert_ctl_arg.vl111n42tuserpagev_user/tocover_observed_deferred_immediate_111htop.t.cover_observed_deferred_immediate_111' 0
C 'ft/t_assert_ctl_arg.vl110n45tuserpagev_user/tocover_final_deferred_immediate_stmt_110htop.t.cover_final_deferred_immediate_stmt_110' 0 C 'ft/t_assert_ctl_arg.vl111n44tuserpagev_user/tocover_final_deferred_immediate_stmt_111htop.t.cover_final_deferred_immediate_stmt_111' 1
C 'ft/t_assert_ctl_arg.vl110n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_110htop.t.cover_observed_deferred_immediate_stmt_110' 0 C 'ft/t_assert_ctl_arg.vl111n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_111htop.t.cover_observed_deferred_immediate_stmt_111' 0
C 'ft/t_assert_ctl_arg.vl112n32tuserpagev_user/tocover_simple_immediate_112htop.t.cover_simple_immediate_112' 1 C 'ft/t_assert_ctl_arg.vl191n21tuserpagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0
C 'ft/t_assert_ctl_arg.vl112n37tuserpagev_user/tocover_simple_immediate_stmt_112htop.t.cover_simple_immediate_stmt_112' 1 C 'ft/t_assert_ctl_arg.vl192n26tuserpagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0
C 'ft/t_assert_ctl_arg.vl112n40tuserpagev_user/tocover_final_deferred_immediate_112htop.t.cover_final_deferred_immediate_112' 1 C 'ft/t_assert_ctl_arg.vl48n30tuserpagev_user/tocover_simple_immediate_48htop.t.cover_simple_immediate_48' 1
C 'ft/t_assert_ctl_arg.vl112n43tuserpagev_user/tocover_observed_deferred_immediate_112htop.t.cover_observed_deferred_immediate_112' 0 C 'ft/t_assert_ctl_arg.vl48n35tuserpagev_user/tocover_simple_immediate_stmt_48htop.t.cover_simple_immediate_stmt_48' 1
C 'ft/t_assert_ctl_arg.vl112n45tuserpagev_user/tocover_final_deferred_immediate_stmt_112htop.t.cover_final_deferred_immediate_stmt_112' 1 C 'ft/t_assert_ctl_arg.vl48n38tuserpagev_user/tocover_final_deferred_immediate_48htop.t.cover_final_deferred_immediate_48' 0
C 'ft/t_assert_ctl_arg.vl112n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_112htop.t.cover_observed_deferred_immediate_stmt_112' 0 C 'ft/t_assert_ctl_arg.vl48n41tuserpagev_user/tocover_observed_deferred_immediate_48htop.t.cover_observed_deferred_immediate_48' 0
C 'ft/t_assert_ctl_arg.vl192n22tuserpagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0 C 'ft/t_assert_ctl_arg.vl48n43tuserpagev_user/tocover_final_deferred_immediate_stmt_48htop.t.cover_final_deferred_immediate_stmt_48' 0
C 'ft/t_assert_ctl_arg.vl193n27tuserpagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0 C 'ft/t_assert_ctl_arg.vl48n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_48htop.t.cover_observed_deferred_immediate_stmt_48' 0
C 'ft/t_assert_ctl_arg.vl49n31tuserpagev_user/tocover_simple_immediate_49htop.t.cover_simple_immediate_49' 1 C 'ft/t_assert_ctl_arg.vl50n30tuserpagev_user/tocover_simple_immediate_50htop.t.cover_simple_immediate_50' 0
C 'ft/t_assert_ctl_arg.vl49n36tuserpagev_user/tocover_simple_immediate_stmt_49htop.t.cover_simple_immediate_stmt_49' 1 C 'ft/t_assert_ctl_arg.vl50n35tuserpagev_user/tocover_simple_immediate_stmt_50htop.t.cover_simple_immediate_stmt_50' 0
C 'ft/t_assert_ctl_arg.vl49n39tuserpagev_user/tocover_final_deferred_immediate_49htop.t.cover_final_deferred_immediate_49' 0 C 'ft/t_assert_ctl_arg.vl50n38tuserpagev_user/tocover_final_deferred_immediate_50htop.t.cover_final_deferred_immediate_50' 0
C 'ft/t_assert_ctl_arg.vl49n42tuserpagev_user/tocover_observed_deferred_immediate_49htop.t.cover_observed_deferred_immediate_49' 0 C 'ft/t_assert_ctl_arg.vl50n41tuserpagev_user/tocover_observed_deferred_immediate_50htop.t.cover_observed_deferred_immediate_50' 0
C 'ft/t_assert_ctl_arg.vl49n44tuserpagev_user/tocover_final_deferred_immediate_stmt_49htop.t.cover_final_deferred_immediate_stmt_49' 0 C 'ft/t_assert_ctl_arg.vl50n43tuserpagev_user/tocover_final_deferred_immediate_stmt_50htop.t.cover_final_deferred_immediate_stmt_50' 0
C 'ft/t_assert_ctl_arg.vl49n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_49htop.t.cover_observed_deferred_immediate_stmt_49' 0 C 'ft/t_assert_ctl_arg.vl50n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_50htop.t.cover_observed_deferred_immediate_stmt_50' 0
C 'ft/t_assert_ctl_arg.vl51n31tuserpagev_user/tocover_simple_immediate_51htop.t.cover_simple_immediate_51' 0 C 'ft/t_assert_ctl_arg.vl55n30tuserpagev_user/tocover_simple_immediate_55htop.t.cover_simple_immediate_55' 0
C 'ft/t_assert_ctl_arg.vl51n36tuserpagev_user/tocover_simple_immediate_stmt_51htop.t.cover_simple_immediate_stmt_51' 0 C 'ft/t_assert_ctl_arg.vl55n35tuserpagev_user/tocover_simple_immediate_stmt_55htop.t.cover_simple_immediate_stmt_55' 0
C 'ft/t_assert_ctl_arg.vl51n39tuserpagev_user/tocover_final_deferred_immediate_51htop.t.cover_final_deferred_immediate_51' 0 C 'ft/t_assert_ctl_arg.vl55n38tuserpagev_user/tocover_final_deferred_immediate_55htop.t.cover_final_deferred_immediate_55' 0
C 'ft/t_assert_ctl_arg.vl51n42tuserpagev_user/tocover_observed_deferred_immediate_51htop.t.cover_observed_deferred_immediate_51' 0 C 'ft/t_assert_ctl_arg.vl55n41tuserpagev_user/tocover_observed_deferred_immediate_55htop.t.cover_observed_deferred_immediate_55' 1
C 'ft/t_assert_ctl_arg.vl51n44tuserpagev_user/tocover_final_deferred_immediate_stmt_51htop.t.cover_final_deferred_immediate_stmt_51' 0 C 'ft/t_assert_ctl_arg.vl55n43tuserpagev_user/tocover_final_deferred_immediate_stmt_55htop.t.cover_final_deferred_immediate_stmt_55' 0
C 'ft/t_assert_ctl_arg.vl51n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_51htop.t.cover_observed_deferred_immediate_stmt_51' 0 C 'ft/t_assert_ctl_arg.vl55n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_55htop.t.cover_observed_deferred_immediate_stmt_55' 1
C 'ft/t_assert_ctl_arg.vl56n31tuserpagev_user/tocover_simple_immediate_56htop.t.cover_simple_immediate_56' 0 C 'ft/t_assert_ctl_arg.vl57n30tuserpagev_user/tocover_simple_immediate_57htop.t.cover_simple_immediate_57' 0
C 'ft/t_assert_ctl_arg.vl56n36tuserpagev_user/tocover_simple_immediate_stmt_56htop.t.cover_simple_immediate_stmt_56' 0 C 'ft/t_assert_ctl_arg.vl57n35tuserpagev_user/tocover_simple_immediate_stmt_57htop.t.cover_simple_immediate_stmt_57' 0
C 'ft/t_assert_ctl_arg.vl56n39tuserpagev_user/tocover_final_deferred_immediate_56htop.t.cover_final_deferred_immediate_56' 0 C 'ft/t_assert_ctl_arg.vl57n38tuserpagev_user/tocover_final_deferred_immediate_57htop.t.cover_final_deferred_immediate_57' 0
C 'ft/t_assert_ctl_arg.vl56n42tuserpagev_user/tocover_observed_deferred_immediate_56htop.t.cover_observed_deferred_immediate_56' 1 C 'ft/t_assert_ctl_arg.vl57n41tuserpagev_user/tocover_observed_deferred_immediate_57htop.t.cover_observed_deferred_immediate_57' 0
C 'ft/t_assert_ctl_arg.vl56n44tuserpagev_user/tocover_final_deferred_immediate_stmt_56htop.t.cover_final_deferred_immediate_stmt_56' 0 C 'ft/t_assert_ctl_arg.vl57n43tuserpagev_user/tocover_final_deferred_immediate_stmt_57htop.t.cover_final_deferred_immediate_stmt_57' 0
C 'ft/t_assert_ctl_arg.vl56n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_56htop.t.cover_observed_deferred_immediate_stmt_56' 1 C 'ft/t_assert_ctl_arg.vl57n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_57htop.t.cover_observed_deferred_immediate_stmt_57' 0
C 'ft/t_assert_ctl_arg.vl58n31tuserpagev_user/tocover_simple_immediate_58htop.t.cover_simple_immediate_58' 0 C 'ft/t_assert_ctl_arg.vl62n30tuserpagev_user/tocover_simple_immediate_62htop.t.cover_simple_immediate_62' 0
C 'ft/t_assert_ctl_arg.vl58n36tuserpagev_user/tocover_simple_immediate_stmt_58htop.t.cover_simple_immediate_stmt_58' 0 C 'ft/t_assert_ctl_arg.vl62n35tuserpagev_user/tocover_simple_immediate_stmt_62htop.t.cover_simple_immediate_stmt_62' 0
C 'ft/t_assert_ctl_arg.vl58n39tuserpagev_user/tocover_final_deferred_immediate_58htop.t.cover_final_deferred_immediate_58' 0 C 'ft/t_assert_ctl_arg.vl62n38tuserpagev_user/tocover_final_deferred_immediate_62htop.t.cover_final_deferred_immediate_62' 1
C 'ft/t_assert_ctl_arg.vl58n42tuserpagev_user/tocover_observed_deferred_immediate_58htop.t.cover_observed_deferred_immediate_58' 0 C 'ft/t_assert_ctl_arg.vl62n41tuserpagev_user/tocover_observed_deferred_immediate_62htop.t.cover_observed_deferred_immediate_62' 0
C 'ft/t_assert_ctl_arg.vl58n44tuserpagev_user/tocover_final_deferred_immediate_stmt_58htop.t.cover_final_deferred_immediate_stmt_58' 0 C 'ft/t_assert_ctl_arg.vl62n43tuserpagev_user/tocover_final_deferred_immediate_stmt_62htop.t.cover_final_deferred_immediate_stmt_62' 1
C 'ft/t_assert_ctl_arg.vl58n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_58htop.t.cover_observed_deferred_immediate_stmt_58' 0 C 'ft/t_assert_ctl_arg.vl62n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_62htop.t.cover_observed_deferred_immediate_stmt_62' 0
C 'ft/t_assert_ctl_arg.vl63n31tuserpagev_user/tocover_simple_immediate_63htop.t.cover_simple_immediate_63' 0 C 'ft/t_assert_ctl_arg.vl64n30tuserpagev_user/tocover_simple_immediate_64htop.t.cover_simple_immediate_64' 0
C 'ft/t_assert_ctl_arg.vl63n36tuserpagev_user/tocover_simple_immediate_stmt_63htop.t.cover_simple_immediate_stmt_63' 0 C 'ft/t_assert_ctl_arg.vl64n35tuserpagev_user/tocover_simple_immediate_stmt_64htop.t.cover_simple_immediate_stmt_64' 0
C 'ft/t_assert_ctl_arg.vl63n39tuserpagev_user/tocover_final_deferred_immediate_63htop.t.cover_final_deferred_immediate_63' 1 C 'ft/t_assert_ctl_arg.vl64n38tuserpagev_user/tocover_final_deferred_immediate_64htop.t.cover_final_deferred_immediate_64' 0
C 'ft/t_assert_ctl_arg.vl63n42tuserpagev_user/tocover_observed_deferred_immediate_63htop.t.cover_observed_deferred_immediate_63' 0 C 'ft/t_assert_ctl_arg.vl64n41tuserpagev_user/tocover_observed_deferred_immediate_64htop.t.cover_observed_deferred_immediate_64' 0
C 'ft/t_assert_ctl_arg.vl63n44tuserpagev_user/tocover_final_deferred_immediate_stmt_63htop.t.cover_final_deferred_immediate_stmt_63' 1 C 'ft/t_assert_ctl_arg.vl64n43tuserpagev_user/tocover_final_deferred_immediate_stmt_64htop.t.cover_final_deferred_immediate_stmt_64' 0
C 'ft/t_assert_ctl_arg.vl63n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_63htop.t.cover_observed_deferred_immediate_stmt_63' 0 C 'ft/t_assert_ctl_arg.vl64n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_64htop.t.cover_observed_deferred_immediate_stmt_64' 0
C 'ft/t_assert_ctl_arg.vl65n31tuserpagev_user/tocover_simple_immediate_65htop.t.cover_simple_immediate_65' 0 C 'ft/t_assert_ctl_arg.vl68n30tuserpagev_user/tocover_simple_immediate_68htop.t.cover_simple_immediate_68' 0
C 'ft/t_assert_ctl_arg.vl65n36tuserpagev_user/tocover_simple_immediate_stmt_65htop.t.cover_simple_immediate_stmt_65' 0 C 'ft/t_assert_ctl_arg.vl68n35tuserpagev_user/tocover_simple_immediate_stmt_68htop.t.cover_simple_immediate_stmt_68' 0
C 'ft/t_assert_ctl_arg.vl65n39tuserpagev_user/tocover_final_deferred_immediate_65htop.t.cover_final_deferred_immediate_65' 0 C 'ft/t_assert_ctl_arg.vl68n38tuserpagev_user/tocover_final_deferred_immediate_68htop.t.cover_final_deferred_immediate_68' 0
C 'ft/t_assert_ctl_arg.vl65n42tuserpagev_user/tocover_observed_deferred_immediate_65htop.t.cover_observed_deferred_immediate_65' 0 C 'ft/t_assert_ctl_arg.vl68n41tuserpagev_user/tocover_observed_deferred_immediate_68htop.t.cover_observed_deferred_immediate_68' 0
C 'ft/t_assert_ctl_arg.vl65n44tuserpagev_user/tocover_final_deferred_immediate_stmt_65htop.t.cover_final_deferred_immediate_stmt_65' 0 C 'ft/t_assert_ctl_arg.vl68n43tuserpagev_user/tocover_final_deferred_immediate_stmt_68htop.t.cover_final_deferred_immediate_stmt_68' 0
C 'ft/t_assert_ctl_arg.vl65n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_65htop.t.cover_observed_deferred_immediate_stmt_65' 0 C 'ft/t_assert_ctl_arg.vl68n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_68htop.t.cover_observed_deferred_immediate_stmt_68' 0
C 'ft/t_assert_ctl_arg.vl69n31tuserpagev_user/tocover_simple_immediate_69htop.t.cover_simple_immediate_69' 0 C 'ft/t_assert_ctl_arg.vl70n30tuserpagev_user/tocover_simple_immediate_70htop.t.cover_simple_immediate_70' 1
C 'ft/t_assert_ctl_arg.vl69n36tuserpagev_user/tocover_simple_immediate_stmt_69htop.t.cover_simple_immediate_stmt_69' 0 C 'ft/t_assert_ctl_arg.vl70n35tuserpagev_user/tocover_simple_immediate_stmt_70htop.t.cover_simple_immediate_stmt_70' 1
C 'ft/t_assert_ctl_arg.vl69n39tuserpagev_user/tocover_final_deferred_immediate_69htop.t.cover_final_deferred_immediate_69' 0 C 'ft/t_assert_ctl_arg.vl70n38tuserpagev_user/tocover_final_deferred_immediate_70htop.t.cover_final_deferred_immediate_70' 1
C 'ft/t_assert_ctl_arg.vl69n42tuserpagev_user/tocover_observed_deferred_immediate_69htop.t.cover_observed_deferred_immediate_69' 0 C 'ft/t_assert_ctl_arg.vl70n41tuserpagev_user/tocover_observed_deferred_immediate_70htop.t.cover_observed_deferred_immediate_70' 1
C 'ft/t_assert_ctl_arg.vl69n44tuserpagev_user/tocover_final_deferred_immediate_stmt_69htop.t.cover_final_deferred_immediate_stmt_69' 0 C 'ft/t_assert_ctl_arg.vl70n43tuserpagev_user/tocover_final_deferred_immediate_stmt_70htop.t.cover_final_deferred_immediate_stmt_70' 1
C 'ft/t_assert_ctl_arg.vl69n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_69htop.t.cover_observed_deferred_immediate_stmt_69' 0 C 'ft/t_assert_ctl_arg.vl70n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_70htop.t.cover_observed_deferred_immediate_stmt_70' 1
C 'ft/t_assert_ctl_arg.vl71n31tuserpagev_user/tocover_simple_immediate_71htop.t.cover_simple_immediate_71' 1 C 'ft/t_assert_ctl_arg.vl72n30tuserpagev_user/tocover_simple_immediate_72htop.t.cover_simple_immediate_72' 0
C 'ft/t_assert_ctl_arg.vl71n36tuserpagev_user/tocover_simple_immediate_stmt_71htop.t.cover_simple_immediate_stmt_71' 1 C 'ft/t_assert_ctl_arg.vl72n35tuserpagev_user/tocover_simple_immediate_stmt_72htop.t.cover_simple_immediate_stmt_72' 0
C 'ft/t_assert_ctl_arg.vl71n39tuserpagev_user/tocover_final_deferred_immediate_71htop.t.cover_final_deferred_immediate_71' 1 C 'ft/t_assert_ctl_arg.vl72n38tuserpagev_user/tocover_final_deferred_immediate_72htop.t.cover_final_deferred_immediate_72' 0
C 'ft/t_assert_ctl_arg.vl71n42tuserpagev_user/tocover_observed_deferred_immediate_71htop.t.cover_observed_deferred_immediate_71' 1 C 'ft/t_assert_ctl_arg.vl72n41tuserpagev_user/tocover_observed_deferred_immediate_72htop.t.cover_observed_deferred_immediate_72' 0
C 'ft/t_assert_ctl_arg.vl71n44tuserpagev_user/tocover_final_deferred_immediate_stmt_71htop.t.cover_final_deferred_immediate_stmt_71' 1 C 'ft/t_assert_ctl_arg.vl72n43tuserpagev_user/tocover_final_deferred_immediate_stmt_72htop.t.cover_final_deferred_immediate_stmt_72' 0
C 'ft/t_assert_ctl_arg.vl71n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_71htop.t.cover_observed_deferred_immediate_stmt_71' 1 C 'ft/t_assert_ctl_arg.vl72n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_72htop.t.cover_observed_deferred_immediate_stmt_72' 0
C 'ft/t_assert_ctl_arg.vl73n31tuserpagev_user/tocover_simple_immediate_73htop.t.cover_simple_immediate_73' 0 C 'ft/t_assert_ctl_arg.vl75n30tuserpagev_user/tocover_simple_immediate_75htop.t.cover_simple_immediate_75' 1
C 'ft/t_assert_ctl_arg.vl73n36tuserpagev_user/tocover_simple_immediate_stmt_73htop.t.cover_simple_immediate_stmt_73' 0 C 'ft/t_assert_ctl_arg.vl75n35tuserpagev_user/tocover_simple_immediate_stmt_75htop.t.cover_simple_immediate_stmt_75' 1
C 'ft/t_assert_ctl_arg.vl73n39tuserpagev_user/tocover_final_deferred_immediate_73htop.t.cover_final_deferred_immediate_73' 0 C 'ft/t_assert_ctl_arg.vl75n38tuserpagev_user/tocover_final_deferred_immediate_75htop.t.cover_final_deferred_immediate_75' 0
C 'ft/t_assert_ctl_arg.vl73n42tuserpagev_user/tocover_observed_deferred_immediate_73htop.t.cover_observed_deferred_immediate_73' 0 C 'ft/t_assert_ctl_arg.vl75n41tuserpagev_user/tocover_observed_deferred_immediate_75htop.t.cover_observed_deferred_immediate_75' 1
C 'ft/t_assert_ctl_arg.vl73n44tuserpagev_user/tocover_final_deferred_immediate_stmt_73htop.t.cover_final_deferred_immediate_stmt_73' 0 C 'ft/t_assert_ctl_arg.vl75n43tuserpagev_user/tocover_final_deferred_immediate_stmt_75htop.t.cover_final_deferred_immediate_stmt_75' 0
C 'ft/t_assert_ctl_arg.vl73n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_73htop.t.cover_observed_deferred_immediate_stmt_73' 0 C 'ft/t_assert_ctl_arg.vl75n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_75htop.t.cover_observed_deferred_immediate_stmt_75' 1
C 'ft/t_assert_ctl_arg.vl76n31tuserpagev_user/tocover_simple_immediate_76htop.t.cover_simple_immediate_76' 1 C 'ft/t_assert_ctl_arg.vl77n30tuserpagev_user/tocover_simple_immediate_77htop.t.cover_simple_immediate_77' 1
C 'ft/t_assert_ctl_arg.vl76n36tuserpagev_user/tocover_simple_immediate_stmt_76htop.t.cover_simple_immediate_stmt_76' 1 C 'ft/t_assert_ctl_arg.vl77n35tuserpagev_user/tocover_simple_immediate_stmt_77htop.t.cover_simple_immediate_stmt_77' 1
C 'ft/t_assert_ctl_arg.vl76n39tuserpagev_user/tocover_final_deferred_immediate_76htop.t.cover_final_deferred_immediate_76' 0 C 'ft/t_assert_ctl_arg.vl77n38tuserpagev_user/tocover_final_deferred_immediate_77htop.t.cover_final_deferred_immediate_77' 1
C 'ft/t_assert_ctl_arg.vl76n42tuserpagev_user/tocover_observed_deferred_immediate_76htop.t.cover_observed_deferred_immediate_76' 1 C 'ft/t_assert_ctl_arg.vl77n41tuserpagev_user/tocover_observed_deferred_immediate_77htop.t.cover_observed_deferred_immediate_77' 1
C 'ft/t_assert_ctl_arg.vl76n44tuserpagev_user/tocover_final_deferred_immediate_stmt_76htop.t.cover_final_deferred_immediate_stmt_76' 0 C 'ft/t_assert_ctl_arg.vl77n43tuserpagev_user/tocover_final_deferred_immediate_stmt_77htop.t.cover_final_deferred_immediate_stmt_77' 1
C 'ft/t_assert_ctl_arg.vl76n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_76htop.t.cover_observed_deferred_immediate_stmt_76' 1 C 'ft/t_assert_ctl_arg.vl77n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_77htop.t.cover_observed_deferred_immediate_stmt_77' 1
C 'ft/t_assert_ctl_arg.vl78n31tuserpagev_user/tocover_simple_immediate_78htop.t.cover_simple_immediate_78' 1 C 'ft/t_assert_ctl_arg.vl79n30tuserpagev_user/tocover_simple_immediate_79htop.t.cover_simple_immediate_79' 1
C 'ft/t_assert_ctl_arg.vl78n36tuserpagev_user/tocover_simple_immediate_stmt_78htop.t.cover_simple_immediate_stmt_78' 1 C 'ft/t_assert_ctl_arg.vl79n35tuserpagev_user/tocover_simple_immediate_stmt_79htop.t.cover_simple_immediate_stmt_79' 1
C 'ft/t_assert_ctl_arg.vl78n39tuserpagev_user/tocover_final_deferred_immediate_78htop.t.cover_final_deferred_immediate_78' 1 C 'ft/t_assert_ctl_arg.vl79n38tuserpagev_user/tocover_final_deferred_immediate_79htop.t.cover_final_deferred_immediate_79' 0
C 'ft/t_assert_ctl_arg.vl78n42tuserpagev_user/tocover_observed_deferred_immediate_78htop.t.cover_observed_deferred_immediate_78' 1 C 'ft/t_assert_ctl_arg.vl79n41tuserpagev_user/tocover_observed_deferred_immediate_79htop.t.cover_observed_deferred_immediate_79' 0
C 'ft/t_assert_ctl_arg.vl78n44tuserpagev_user/tocover_final_deferred_immediate_stmt_78htop.t.cover_final_deferred_immediate_stmt_78' 1 C 'ft/t_assert_ctl_arg.vl79n43tuserpagev_user/tocover_final_deferred_immediate_stmt_79htop.t.cover_final_deferred_immediate_stmt_79' 0
C 'ft/t_assert_ctl_arg.vl78n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_78htop.t.cover_observed_deferred_immediate_stmt_78' 1 C 'ft/t_assert_ctl_arg.vl79n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_79htop.t.cover_observed_deferred_immediate_stmt_79' 0
C 'ft/t_assert_ctl_arg.vl80n31tuserpagev_user/tocover_simple_immediate_80htop.t.cover_simple_immediate_80' 1 C 'ft/t_assert_ctl_arg.vl81n30tuserpagev_user/tocover_simple_immediate_81htop.t.cover_simple_immediate_81' 1
C 'ft/t_assert_ctl_arg.vl80n36tuserpagev_user/tocover_simple_immediate_stmt_80htop.t.cover_simple_immediate_stmt_80' 1 C 'ft/t_assert_ctl_arg.vl81n35tuserpagev_user/tocover_simple_immediate_stmt_81htop.t.cover_simple_immediate_stmt_81' 1
C 'ft/t_assert_ctl_arg.vl80n39tuserpagev_user/tocover_final_deferred_immediate_80htop.t.cover_final_deferred_immediate_80' 0 C 'ft/t_assert_ctl_arg.vl81n38tuserpagev_user/tocover_final_deferred_immediate_81htop.t.cover_final_deferred_immediate_81' 0
C 'ft/t_assert_ctl_arg.vl80n42tuserpagev_user/tocover_observed_deferred_immediate_80htop.t.cover_observed_deferred_immediate_80' 0 C 'ft/t_assert_ctl_arg.vl81n41tuserpagev_user/tocover_observed_deferred_immediate_81htop.t.cover_observed_deferred_immediate_81' 0
C 'ft/t_assert_ctl_arg.vl80n44tuserpagev_user/tocover_final_deferred_immediate_stmt_80htop.t.cover_final_deferred_immediate_stmt_80' 0 C 'ft/t_assert_ctl_arg.vl81n43tuserpagev_user/tocover_final_deferred_immediate_stmt_81htop.t.cover_final_deferred_immediate_stmt_81' 0
C 'ft/t_assert_ctl_arg.vl80n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_80htop.t.cover_observed_deferred_immediate_stmt_80' 0 C 'ft/t_assert_ctl_arg.vl81n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_81htop.t.cover_observed_deferred_immediate_stmt_81' 0
C 'ft/t_assert_ctl_arg.vl82n31tuserpagev_user/tocover_simple_immediate_82htop.t.cover_simple_immediate_82' 1 C 'ft/t_assert_ctl_arg.vl83n30tuserpagev_user/tocover_simple_immediate_83htop.t.cover_simple_immediate_83' 0
C 'ft/t_assert_ctl_arg.vl82n36tuserpagev_user/tocover_simple_immediate_stmt_82htop.t.cover_simple_immediate_stmt_82' 1 C 'ft/t_assert_ctl_arg.vl83n35tuserpagev_user/tocover_simple_immediate_stmt_83htop.t.cover_simple_immediate_stmt_83' 0
C 'ft/t_assert_ctl_arg.vl82n39tuserpagev_user/tocover_final_deferred_immediate_82htop.t.cover_final_deferred_immediate_82' 0 C 'ft/t_assert_ctl_arg.vl83n38tuserpagev_user/tocover_final_deferred_immediate_83htop.t.cover_final_deferred_immediate_83' 0
C 'ft/t_assert_ctl_arg.vl82n42tuserpagev_user/tocover_observed_deferred_immediate_82htop.t.cover_observed_deferred_immediate_82' 0 C 'ft/t_assert_ctl_arg.vl83n41tuserpagev_user/tocover_observed_deferred_immediate_83htop.t.cover_observed_deferred_immediate_83' 0
C 'ft/t_assert_ctl_arg.vl82n44tuserpagev_user/tocover_final_deferred_immediate_stmt_82htop.t.cover_final_deferred_immediate_stmt_82' 0 C 'ft/t_assert_ctl_arg.vl83n43tuserpagev_user/tocover_final_deferred_immediate_stmt_83htop.t.cover_final_deferred_immediate_stmt_83' 0
C 'ft/t_assert_ctl_arg.vl82n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_82htop.t.cover_observed_deferred_immediate_stmt_82' 0 C 'ft/t_assert_ctl_arg.vl83n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_83htop.t.cover_observed_deferred_immediate_stmt_83' 0
C 'ft/t_assert_ctl_arg.vl84n31tuserpagev_user/tocover_simple_immediate_84htop.t.cover_simple_immediate_84' 0 C 'ft/t_assert_ctl_arg.vl85n30tuserpagev_user/tocover_simple_immediate_85htop.t.cover_simple_immediate_85' 1
C 'ft/t_assert_ctl_arg.vl84n36tuserpagev_user/tocover_simple_immediate_stmt_84htop.t.cover_simple_immediate_stmt_84' 0 C 'ft/t_assert_ctl_arg.vl85n35tuserpagev_user/tocover_simple_immediate_stmt_85htop.t.cover_simple_immediate_stmt_85' 1
C 'ft/t_assert_ctl_arg.vl84n39tuserpagev_user/tocover_final_deferred_immediate_84htop.t.cover_final_deferred_immediate_84' 0 C 'ft/t_assert_ctl_arg.vl85n38tuserpagev_user/tocover_final_deferred_immediate_85htop.t.cover_final_deferred_immediate_85' 0
C 'ft/t_assert_ctl_arg.vl84n42tuserpagev_user/tocover_observed_deferred_immediate_84htop.t.cover_observed_deferred_immediate_84' 0 C 'ft/t_assert_ctl_arg.vl85n41tuserpagev_user/tocover_observed_deferred_immediate_85htop.t.cover_observed_deferred_immediate_85' 0
C 'ft/t_assert_ctl_arg.vl84n44tuserpagev_user/tocover_final_deferred_immediate_stmt_84htop.t.cover_final_deferred_immediate_stmt_84' 0 C 'ft/t_assert_ctl_arg.vl85n43tuserpagev_user/tocover_final_deferred_immediate_stmt_85htop.t.cover_final_deferred_immediate_stmt_85' 0
C 'ft/t_assert_ctl_arg.vl84n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_84htop.t.cover_observed_deferred_immediate_stmt_84' 0 C 'ft/t_assert_ctl_arg.vl85n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_85htop.t.cover_observed_deferred_immediate_stmt_85' 0
C 'ft/t_assert_ctl_arg.vl86n31tuserpagev_user/tocover_simple_immediate_86htop.t.cover_simple_immediate_86' 1 C 'ft/t_assert_ctl_arg.vl87n30tuserpagev_user/tocover_simple_immediate_87htop.t.cover_simple_immediate_87' 0
C 'ft/t_assert_ctl_arg.vl86n36tuserpagev_user/tocover_simple_immediate_stmt_86htop.t.cover_simple_immediate_stmt_86' 1 C 'ft/t_assert_ctl_arg.vl87n35tuserpagev_user/tocover_simple_immediate_stmt_87htop.t.cover_simple_immediate_stmt_87' 0
C 'ft/t_assert_ctl_arg.vl86n39tuserpagev_user/tocover_final_deferred_immediate_86htop.t.cover_final_deferred_immediate_86' 0 C 'ft/t_assert_ctl_arg.vl87n38tuserpagev_user/tocover_final_deferred_immediate_87htop.t.cover_final_deferred_immediate_87' 0
C 'ft/t_assert_ctl_arg.vl86n42tuserpagev_user/tocover_observed_deferred_immediate_86htop.t.cover_observed_deferred_immediate_86' 0 C 'ft/t_assert_ctl_arg.vl87n41tuserpagev_user/tocover_observed_deferred_immediate_87htop.t.cover_observed_deferred_immediate_87' 0
C 'ft/t_assert_ctl_arg.vl86n44tuserpagev_user/tocover_final_deferred_immediate_stmt_86htop.t.cover_final_deferred_immediate_stmt_86' 0 C 'ft/t_assert_ctl_arg.vl87n43tuserpagev_user/tocover_final_deferred_immediate_stmt_87htop.t.cover_final_deferred_immediate_stmt_87' 0
C 'ft/t_assert_ctl_arg.vl86n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_86htop.t.cover_observed_deferred_immediate_stmt_86' 0 C 'ft/t_assert_ctl_arg.vl87n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_87htop.t.cover_observed_deferred_immediate_stmt_87' 0
C 'ft/t_assert_ctl_arg.vl88n31tuserpagev_user/tocover_simple_immediate_88htop.t.cover_simple_immediate_88' 0 C 'ft/t_assert_ctl_arg.vl89n30tuserpagev_user/tocover_simple_immediate_89htop.t.cover_simple_immediate_89' 1
C 'ft/t_assert_ctl_arg.vl88n36tuserpagev_user/tocover_simple_immediate_stmt_88htop.t.cover_simple_immediate_stmt_88' 0 C 'ft/t_assert_ctl_arg.vl89n35tuserpagev_user/tocover_simple_immediate_stmt_89htop.t.cover_simple_immediate_stmt_89' 1
C 'ft/t_assert_ctl_arg.vl88n39tuserpagev_user/tocover_final_deferred_immediate_88htop.t.cover_final_deferred_immediate_88' 0 C 'ft/t_assert_ctl_arg.vl89n38tuserpagev_user/tocover_final_deferred_immediate_89htop.t.cover_final_deferred_immediate_89' 1
C 'ft/t_assert_ctl_arg.vl88n42tuserpagev_user/tocover_observed_deferred_immediate_88htop.t.cover_observed_deferred_immediate_88' 0 C 'ft/t_assert_ctl_arg.vl89n41tuserpagev_user/tocover_observed_deferred_immediate_89htop.t.cover_observed_deferred_immediate_89' 1
C 'ft/t_assert_ctl_arg.vl88n44tuserpagev_user/tocover_final_deferred_immediate_stmt_88htop.t.cover_final_deferred_immediate_stmt_88' 0 C 'ft/t_assert_ctl_arg.vl89n43tuserpagev_user/tocover_final_deferred_immediate_stmt_89htop.t.cover_final_deferred_immediate_stmt_89' 1
C 'ft/t_assert_ctl_arg.vl88n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_88htop.t.cover_observed_deferred_immediate_stmt_88' 0 C 'ft/t_assert_ctl_arg.vl89n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_89htop.t.cover_observed_deferred_immediate_stmt_89' 1
C 'ft/t_assert_ctl_arg.vl90n31tuserpagev_user/tocover_simple_immediate_90htop.t.cover_simple_immediate_90' 1 C 'ft/t_assert_ctl_arg.vl91n30tuserpagev_user/tocover_simple_immediate_91htop.t.cover_simple_immediate_91' 0
C 'ft/t_assert_ctl_arg.vl90n36tuserpagev_user/tocover_simple_immediate_stmt_90htop.t.cover_simple_immediate_stmt_90' 1 C 'ft/t_assert_ctl_arg.vl91n35tuserpagev_user/tocover_simple_immediate_stmt_91htop.t.cover_simple_immediate_stmt_91' 0
C 'ft/t_assert_ctl_arg.vl90n39tuserpagev_user/tocover_final_deferred_immediate_90htop.t.cover_final_deferred_immediate_90' 1 C 'ft/t_assert_ctl_arg.vl91n38tuserpagev_user/tocover_final_deferred_immediate_91htop.t.cover_final_deferred_immediate_91' 0
C 'ft/t_assert_ctl_arg.vl90n42tuserpagev_user/tocover_observed_deferred_immediate_90htop.t.cover_observed_deferred_immediate_90' 1 C 'ft/t_assert_ctl_arg.vl91n41tuserpagev_user/tocover_observed_deferred_immediate_91htop.t.cover_observed_deferred_immediate_91' 0
C 'ft/t_assert_ctl_arg.vl90n44tuserpagev_user/tocover_final_deferred_immediate_stmt_90htop.t.cover_final_deferred_immediate_stmt_90' 1 C 'ft/t_assert_ctl_arg.vl91n43tuserpagev_user/tocover_final_deferred_immediate_stmt_91htop.t.cover_final_deferred_immediate_stmt_91' 0
C 'ft/t_assert_ctl_arg.vl90n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_90htop.t.cover_observed_deferred_immediate_stmt_90' 1 C 'ft/t_assert_ctl_arg.vl91n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_91htop.t.cover_observed_deferred_immediate_stmt_91' 0
C 'ft/t_assert_ctl_arg.vl92n31tuserpagev_user/tocover_simple_immediate_92htop.t.cover_simple_immediate_92' 0 C 'ft/t_assert_ctl_arg.vl96n30tuserpagev_user/tocover_simple_immediate_96htop.t.cover_simple_immediate_96' 0
C 'ft/t_assert_ctl_arg.vl92n36tuserpagev_user/tocover_simple_immediate_stmt_92htop.t.cover_simple_immediate_stmt_92' 0 C 'ft/t_assert_ctl_arg.vl96n35tuserpagev_user/tocover_simple_immediate_stmt_96htop.t.cover_simple_immediate_stmt_96' 0
C 'ft/t_assert_ctl_arg.vl92n39tuserpagev_user/tocover_final_deferred_immediate_92htop.t.cover_final_deferred_immediate_92' 0 C 'ft/t_assert_ctl_arg.vl96n38tuserpagev_user/tocover_final_deferred_immediate_96htop.t.cover_final_deferred_immediate_96' 0
C 'ft/t_assert_ctl_arg.vl92n42tuserpagev_user/tocover_observed_deferred_immediate_92htop.t.cover_observed_deferred_immediate_92' 0 C 'ft/t_assert_ctl_arg.vl96n41tuserpagev_user/tocover_observed_deferred_immediate_96htop.t.cover_observed_deferred_immediate_96' 0
C 'ft/t_assert_ctl_arg.vl92n44tuserpagev_user/tocover_final_deferred_immediate_stmt_92htop.t.cover_final_deferred_immediate_stmt_92' 0 C 'ft/t_assert_ctl_arg.vl96n43tuserpagev_user/tocover_final_deferred_immediate_stmt_96htop.t.cover_final_deferred_immediate_stmt_96' 0
C 'ft/t_assert_ctl_arg.vl92n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_92htop.t.cover_observed_deferred_immediate_stmt_92' 0 C 'ft/t_assert_ctl_arg.vl96n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_96htop.t.cover_observed_deferred_immediate_stmt_96' 0
C 'ft/t_assert_ctl_arg.vl97n31tuserpagev_user/tocover_simple_immediate_97htop.t.cover_simple_immediate_97' 0 C 'ft/t_assert_ctl_arg.vl99n30tuserpagev_user/tocover_simple_immediate_99htop.t.cover_simple_immediate_99' 1
C 'ft/t_assert_ctl_arg.vl97n36tuserpagev_user/tocover_simple_immediate_stmt_97htop.t.cover_simple_immediate_stmt_97' 0 C 'ft/t_assert_ctl_arg.vl99n35tuserpagev_user/tocover_simple_immediate_stmt_99htop.t.cover_simple_immediate_stmt_99' 1
C 'ft/t_assert_ctl_arg.vl97n39tuserpagev_user/tocover_final_deferred_immediate_97htop.t.cover_final_deferred_immediate_97' 0 C 'ft/t_assert_ctl_arg.vl99n38tuserpagev_user/tocover_final_deferred_immediate_99htop.t.cover_final_deferred_immediate_99' 1
C 'ft/t_assert_ctl_arg.vl97n42tuserpagev_user/tocover_observed_deferred_immediate_97htop.t.cover_observed_deferred_immediate_97' 0 C 'ft/t_assert_ctl_arg.vl99n41tuserpagev_user/tocover_observed_deferred_immediate_99htop.t.cover_observed_deferred_immediate_99' 1
C 'ft/t_assert_ctl_arg.vl97n44tuserpagev_user/tocover_final_deferred_immediate_stmt_97htop.t.cover_final_deferred_immediate_stmt_97' 0 C 'ft/t_assert_ctl_arg.vl99n43tuserpagev_user/tocover_final_deferred_immediate_stmt_99htop.t.cover_final_deferred_immediate_stmt_99' 1
C 'ft/t_assert_ctl_arg.vl97n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_97htop.t.cover_observed_deferred_immediate_stmt_97' 0 C 'ft/t_assert_ctl_arg.vl99n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_99htop.t.cover_observed_deferred_immediate_stmt_99' 1

726
test_regress/t/t_assert_ctl_arg.out
View File

@ -1,416 +1,416 @@
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:49 Running all asserts at: t/t_assert_ctl_arg.v:48
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:49 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:48
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
-Info: t/t_assert_ctl_arg.v:137: Verilog $stop, ignored due to +verilator+error+limit -Info: t/t_assert_ctl_arg.v:136: Verilog $stop, ignored due to +verilator+error+limit
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:49 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:48
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:48
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:49 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:48
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:49 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:48
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:48
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:49 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:48
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:49 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:48
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:49 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:48
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:49 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:48
Passed 'top.t.cover_simple_immediate_stmt_49' at t/t_assert_ctl_arg.v:49 Passed 'top.t.cover_simple_immediate_stmt_48' at t/t_assert_ctl_arg.v:48
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:51 Running all asserts at: t/t_assert_ctl_arg.v:50
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:51 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:50
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:51 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:50
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:51 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:50
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:51 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:50
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:51 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:50
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:51 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:50
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:56 Running all asserts at: t/t_assert_ctl_arg.v:55
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:56 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:55
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:56 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:55
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:56 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:55
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:55
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:55
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:56 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:55
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:55
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:55
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:56 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:55
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:56 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:55
Passed 'top.t.cover_observed_deferred_immediate_stmt_56' at t/t_assert_ctl_arg.v:56 Passed 'top.t.cover_observed_deferred_immediate_stmt_55' at t/t_assert_ctl_arg.v:55
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:58 Running all asserts at: t/t_assert_ctl_arg.v:57
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:58 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:57
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:58 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:57
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:58 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:57
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:58 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:57
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:58 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:57
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:58 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:57
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:63 Running all asserts at: t/t_assert_ctl_arg.v:62
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:63 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:62
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:63 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:62
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:63 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:62
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:63 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:62
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:63 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:62
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:62
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:62
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:63 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:62
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:62
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:62
Passed 'top.t.cover_final_deferred_immediate_stmt_63' at t/t_assert_ctl_arg.v:63 Passed 'top.t.cover_final_deferred_immediate_stmt_62' at t/t_assert_ctl_arg.v:62
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:65 Running all asserts at: t/t_assert_ctl_arg.v:64
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:65 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:64
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:65 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:64
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:65 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:64
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:65 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:64
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:65 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:64
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:65 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:64
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:69 Running all asserts at: t/t_assert_ctl_arg.v:68
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:69 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:68
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:69 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:68
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:69 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:68
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:69 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:68
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:69 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:68
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:69 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:68
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:71 Running all asserts at: t/t_assert_ctl_arg.v:70
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:71 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:71 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:71 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:71 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:71 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:71 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:70
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:70
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70
Passed 'top.t.cover_simple_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 Passed 'top.t.cover_simple_immediate_stmt_70' at t/t_assert_ctl_arg.v:70
Passed 'top.t.cover_observed_deferred_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 Passed 'top.t.cover_observed_deferred_immediate_stmt_70' at t/t_assert_ctl_arg.v:70
Passed 'top.t.cover_final_deferred_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 Passed 'top.t.cover_final_deferred_immediate_stmt_70' at t/t_assert_ctl_arg.v:70
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:73 Running all asserts at: t/t_assert_ctl_arg.v:72
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:73 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:72
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:73 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:72
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:73 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:72
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:73 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:72
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:73 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:72
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:73 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:72
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:76 Running all asserts at: t/t_assert_ctl_arg.v:75
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:76 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:75
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:75
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:75
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:76 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:75
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:75
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:75
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:76 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:75
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:75
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:75
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:76 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:75
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:75
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:75
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:76 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:75
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:76 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:75
Passed 'top.t.cover_simple_immediate_stmt_76' at t/t_assert_ctl_arg.v:76 Passed 'top.t.cover_simple_immediate_stmt_75' at t/t_assert_ctl_arg.v:75
Passed 'top.t.cover_observed_deferred_immediate_stmt_76' at t/t_assert_ctl_arg.v:76 Passed 'top.t.cover_observed_deferred_immediate_stmt_75' at t/t_assert_ctl_arg.v:75
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:78 Running all asserts at: t/t_assert_ctl_arg.v:77
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:78 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:78 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:78 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:78 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:78 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:78 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:77
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:77
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77
Passed 'top.t.cover_simple_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 Passed 'top.t.cover_simple_immediate_stmt_77' at t/t_assert_ctl_arg.v:77
Passed 'top.t.cover_observed_deferred_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 Passed 'top.t.cover_observed_deferred_immediate_stmt_77' at t/t_assert_ctl_arg.v:77
Passed 'top.t.cover_final_deferred_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 Passed 'top.t.cover_final_deferred_immediate_stmt_77' at t/t_assert_ctl_arg.v:77
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:80 Running all asserts at: t/t_assert_ctl_arg.v:79
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:80 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:79
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:80 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:79
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:79
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:80 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:79
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:80 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:79
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:79
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:80 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:79
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:80 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:79
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:80 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:79
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:80 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:79
Passed 'top.t.cover_simple_immediate_stmt_80' at t/t_assert_ctl_arg.v:80 Passed 'top.t.cover_simple_immediate_stmt_79' at t/t_assert_ctl_arg.v:79
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:82 Running all asserts at: t/t_assert_ctl_arg.v:81
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:82 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:81
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:82 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:81
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:81
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:82 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:81
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:82 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:81
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:81
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:82 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:81
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:82 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:81
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:82 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:81
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:82 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:81
Passed 'top.t.cover_simple_immediate_stmt_82' at t/t_assert_ctl_arg.v:82 Passed 'top.t.cover_simple_immediate_stmt_81' at t/t_assert_ctl_arg.v:81
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:84 Running all asserts at: t/t_assert_ctl_arg.v:83
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:84 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:83
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:84 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:83
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:84 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:83
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:84 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:83
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:84 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:83
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:84 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:83
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:86 Running all asserts at: t/t_assert_ctl_arg.v:85
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:86 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:85
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:86 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:85
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:85
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:86 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:85
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:86 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:85
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:85
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:86 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:85
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:86 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:85
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:86 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:85
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:86 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:85
Passed 'top.t.cover_simple_immediate_stmt_86' at t/t_assert_ctl_arg.v:86 Passed 'top.t.cover_simple_immediate_stmt_85' at t/t_assert_ctl_arg.v:85
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:88 Running all asserts at: t/t_assert_ctl_arg.v:87
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:88 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:87
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:88 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:87
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:88 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:87
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:88 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:87
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:88 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:87
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:88 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:87
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:90 Running all asserts at: t/t_assert_ctl_arg.v:89
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:90 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:90 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:90 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:90 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:90 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:90 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:89
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:89
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89
Passed 'top.t.cover_simple_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 Passed 'top.t.cover_simple_immediate_stmt_89' at t/t_assert_ctl_arg.v:89
Passed 'top.t.cover_observed_deferred_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 Passed 'top.t.cover_observed_deferred_immediate_stmt_89' at t/t_assert_ctl_arg.v:89
Passed 'top.t.cover_final_deferred_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 Passed 'top.t.cover_final_deferred_immediate_stmt_89' at t/t_assert_ctl_arg.v:89
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:92 Running all asserts at: t/t_assert_ctl_arg.v:91
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:92 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:91
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:92 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:91
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:92 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:91
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:92 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:91
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:92 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:91
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:92 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:91
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:97 Running all asserts at: t/t_assert_ctl_arg.v:96
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:97 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:96
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:96
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:96
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:97 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:96
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:97 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:96
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:96
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:96
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:97 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:96
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:97 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:96
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:96
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:96
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:97 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:96
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:100 Running all asserts at: t/t_assert_ctl_arg.v:99
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:100 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:99
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:100 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:99
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:100 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:99
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:100 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:99
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:100 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:99
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:100 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:99
Passed 'top.t.cover_simple_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 Passed 'top.t.cover_simple_immediate_stmt_99' at t/t_assert_ctl_arg.v:99
Passed 'top.t.cover_observed_deferred_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 Passed 'top.t.cover_observed_deferred_immediate_stmt_99' at t/t_assert_ctl_arg.v:99
Passed 'top.t.cover_final_deferred_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 Passed 'top.t.cover_final_deferred_immediate_stmt_99' at t/t_assert_ctl_arg.v:99
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:103 Running all asserts at: t/t_assert_ctl_arg.v:102
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:103 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:102
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:103 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:102
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:102
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:102
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:103 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:102
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:103 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:102
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:102
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:102
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:103 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:102
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:103 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:102
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:102
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:102
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:106 Running all asserts at: t/t_assert_ctl_arg.v:105
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:106 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:105
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:105
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:105
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:106 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:105
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:106 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:105
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:105
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:105
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:106 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:105
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:106 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:105
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:105
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:105
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:106 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:105
Passed 'top.t.cover_simple_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 Passed 'top.t.cover_simple_immediate_stmt_105' at t/t_assert_ctl_arg.v:105
Passed 'top.t.cover_observed_deferred_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 Passed 'top.t.cover_observed_deferred_immediate_stmt_105' at t/t_assert_ctl_arg.v:105
Passed 'top.t.cover_final_deferred_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 Passed 'top.t.cover_final_deferred_immediate_stmt_105' at t/t_assert_ctl_arg.v:105
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:108 Running all asserts at: t/t_assert_ctl_arg.v:107
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:108 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:108 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:108 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:108 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:108 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:108 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:107
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:107
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107
Passed 'top.t.cover_simple_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 Passed 'top.t.cover_simple_immediate_stmt_107' at t/t_assert_ctl_arg.v:107
Passed 'top.t.cover_observed_deferred_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 Passed 'top.t.cover_observed_deferred_immediate_stmt_107' at t/t_assert_ctl_arg.v:107
Passed 'top.t.cover_final_deferred_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 Passed 'top.t.cover_final_deferred_immediate_stmt_107' at t/t_assert_ctl_arg.v:107
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:110 Running all asserts at: t/t_assert_ctl_arg.v:109
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:110 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:109
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:110 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:109
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:110 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:109
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:110 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:109
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:110 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:109
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:110 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:109
========== ==========
Running all asserts at: t/t_assert_ctl_arg.v:112 Running all asserts at: t/t_assert_ctl_arg.v:111
========== ==========
Testing assert_simple_immediate at t/t_assert_ctl_arg.v:112 Testing assert_simple_immediate at t/t_assert_ctl_arg.v:111
Testing assume_simple_immediate at t/t_assert_ctl_arg.v:112 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:111
[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed.
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:112 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:111
Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:112 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:111
Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:112 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:111
Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:112 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:111
Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:112 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:111
Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:112 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:111
[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. [0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed.
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:112 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:111
Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:112 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:111
Passed 'top.t.cover_simple_immediate_stmt_112' at t/t_assert_ctl_arg.v:112 Passed 'top.t.cover_simple_immediate_stmt_111' at t/t_assert_ctl_arg.v:111
Passed 'top.t.cover_final_deferred_immediate_stmt_112' at t/t_assert_ctl_arg.v:112 Passed 'top.t.cover_final_deferred_immediate_stmt_111' at t/t_assert_ctl_arg.v:111
Disabling concurrent asserts, time: 10 Disabling concurrent asserts, time: 10
Enabling concurrent asserts, time: 20 Enabling concurrent asserts, time: 20
*-* All Finished *-* *-* All Finished *-*
[20] %Error: t_assert_ctl_arg.v:182: Assertion failed in top.t.concurrent.assert_concurrent: 'assert' failed. [20] %Error: t_assert_ctl_arg.v:181: Assertion failed in top.t.concurrent.assert_concurrent: 'assert' failed.
Failed 'top.t.concurrent.assert_concurrent_else' at t/t_assert_ctl_arg.v:183 Failed 'top.t.concurrent.assert_concurrent_else' at t/t_assert_ctl_arg.v:182
Failed 'top.t.concurrent.assert_concurrent_stmt_else' at t/t_assert_ctl_arg.v:185 Failed 'top.t.concurrent.assert_concurrent_stmt_else' at t/t_assert_ctl_arg.v:184
[20] %Error: t_assert_ctl_arg.v:187: Assertion failed in top.t.concurrent.assume_concurrent: 'assert' failed. [20] %Error: t_assert_ctl_arg.v:186: Assertion failed in top.t.concurrent.assume_concurrent: 'assert' failed.
Failed 'top.t.concurrent.assume_concurrent_else' at t/t_assert_ctl_arg.v:188 Failed 'top.t.concurrent.assume_concurrent_else' at t/t_assert_ctl_arg.v:187
Failed 'top.t.concurrent.assume_concurrent_stmt_else' at t/t_assert_ctl_arg.v:190 Failed 'top.t.concurrent.assume_concurrent_stmt_else' at t/t_assert_ctl_arg.v:189

7
test_regress/t/t_assert_ctl_arg.v
View File

@ -20,10 +20,9 @@
cover_final_deferred_immediate_`__LINE__: cover final (1); \ cover_final_deferred_immediate_`__LINE__: cover final (1); \
cover_final_deferred_immediate_stmt_`__LINE__: cover final (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ cover_final_deferred_immediate_stmt_`__LINE__: cover final (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \
module t (/*AUTOARG*/ module t (
clk input clk
); );
input clk;
let On = 3; let On = 3;
let Off = 4; let Off = 4;

8
test_regress/t/t_assert_ctl_arg_unsup.out
View File

@ -1,17 +1,17 @@
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:15:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:15:5: Unsupported: assert control assertion_type
: ... note: In instance 't' : ... note: In instance 't'
15 | $assertcontrol(OFF, EXPECT); 15 | $assertcontrol(OFF, EXPECT);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:16:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:16:5: Unsupported: assert control assertion_type
: ... note: In instance 't' : ... note: In instance 't'
16 | $assertcontrol(OFF, UNIQUE); 16 | $assertcontrol(OFF, UNIQUE);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:17:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:17:5: Unsupported: assert control assertion_type
: ... note: In instance 't' : ... note: In instance 't'
17 | $assertcontrol(OFF, UNIQUE0); 17 | $assertcontrol(OFF, UNIQUE0);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:18:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:18:5: Unsupported: assert control assertion_type
: ... note: In instance 't' : ... note: In instance 't'
18 | $assertcontrol(OFF, PRIORITY); 18 | $assertcontrol(OFF, PRIORITY);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~

14
test_regress/t/t_assert_ctl_concurrent.v
View File

@ -12,21 +12,15 @@ module t;
initial begin initial begin
$assertkill; $assertkill;
#10 #10 reset = 1'b1;
reset = 1'b1;
$display("%t: deassert reset %d", $time, reset); $display("%t: deassert reset %d", $time, reset);
#40 #40 $asserton;
$asserton;
reset = 1'b0; reset = 1'b0;
$display("%t: deassert reset %d", $time, reset); $display("%t: deassert reset %d", $time, reset);
#200 #200 $display("%t: finish", $time);
$display("%t: finish", $time);
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
@ -37,7 +31,7 @@ module t;
always @(posedge clock) if (reset) r <= 1'b1; always @(posedge clock) if (reset) r <= 1'b1;
assert_test: assert_test :
assert property (@(posedge clock) (reset | r)) assert property (@(posedge clock) (reset | r))
else $error("%t: assertion triggered", $time); else $error("%t: assertion triggered", $time);

10
test_regress/t/t_assert_ctl_immediate.out
View File

@ -1,6 +1,6 @@
[0] %Error: t_assert_ctl_immediate.v:47: Assertion failed in top.t.module_with_assertctl: 'assert' failed. [0] %Error: t_assert_ctl_immediate.v:51: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
-Info: t/t_assert_ctl_immediate.v:47: Verilog $stop, ignored due to +verilator+error+limit -Info: t/t_assert_ctl_immediate.v:51: Verilog $stop, ignored due to +verilator+error+limit
[0] %Error: t_assert_ctl_immediate.v:53: Assertion failed in top.t.module_with_assertctl: 'assert' failed. [0] %Error: t_assert_ctl_immediate.v:57: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
[0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. [0] %Error: t_assert_ctl_immediate.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
[0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. [0] %Error: t_assert_ctl_immediate.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
*-* All Finished *-* *-* All Finished *-*

46
test_regress/t/t_assert_ctl_immediate.v
View File

@ -4,53 +4,57 @@
// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-FileCopyrightText: 2024 Antmicro
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk; module_with_assert module_with_assert (clk);
module_with_assertctl module_with_assertctl (clk);
module_with_assert module_with_assert(clk); always @(posedge clk) begin
module_with_assertctl module_with_assertctl(clk); assert (0);
always @ (posedge clk) begin
assert(0);
end end
always @ (negedge clk) begin always @(negedge clk) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
endmodule endmodule
module module_with_assert(input clk); module module_with_assert (
always @(posedge clk) assert(0); input clk
);
always @(posedge clk) assert (0);
endmodule endmodule
module module_with_assertctl(input clk); module module_with_assertctl (
function void assert_off; begin input clk
);
function void assert_off;
begin
$assertoff; $assertoff;
end end
endfunction endfunction
function void assert_on; begin function void assert_on;
begin
$asserton; $asserton;
end end
endfunction endfunction
function void f_assert; begin function void f_assert;
assert(0); begin
assert (0);
end end
endfunction endfunction
initial begin initial begin
assert_on(); assert_on();
assert(0); assert (0);
assert_off(); assert_off();
assert_off(); assert_off();
assert(0); assert (0);
assert_on(); assert_on();
assert_on(); assert_on();
assert(0); assert (0);
f_assert(); f_assert();
f_assert(); f_assert();

64
test_regress/t/t_assert_ctl_unsup.out
View File

@ -1,122 +1,122 @@
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:7: Unsupported: non-constant assert assertion-type expression %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:5: Unsupported: non-constant assert assertion-type expression
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
25 | $assertcontrol(Lock, a); 25 | $assertcontrol(Lock, a);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:27:7: Unsupported: $assertcontrol control_type '2' %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:27:5: Unsupported: $assertcontrol control_type '2'
27 | $assertcontrol(Unlock); 27 | $assertcontrol(Unlock);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:29:7: Unsupported: $assertcontrol control_type '6' %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:29:5: Unsupported: $assertcontrol control_type '6'
29 | $assertcontrol(PassOn); 29 | $assertcontrol(PassOn);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:30:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:30:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
30 | $assertpasson; 30 | $assertpasson;
| ^~~~~~~~~~~~~ | ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:31:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:31:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
31 | $assertpasson(a); 31 | $assertpasson(a);
| ^~~~~~~~~~~~~ | ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
32 | $assertpasson(a, t); 32 | $assertpasson(a, t);
| ^~~~~~~~~~~~~ | ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:34:7: Unsupported: $assertcontrol control_type '7' %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:34:5: Unsupported: $assertcontrol control_type '7'
34 | $assertcontrol(PassOff); 34 | $assertcontrol(PassOff);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:35:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:35:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
35 | $assertpassoff; 35 | $assertpassoff;
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:36:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:36:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
36 | $assertpassoff(a); 36 | $assertpassoff(a);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:37:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:37:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
37 | $assertpassoff(a, t); 37 | $assertpassoff(a, t);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:39:7: Unsupported: $assertcontrol control_type '8' %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:39:5: Unsupported: $assertcontrol control_type '8'
39 | $assertcontrol(FailOn); 39 | $assertcontrol(FailOn);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:40:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:40:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
40 | $assertfailon; 40 | $assertfailon;
| ^~~~~~~~~~~~~ | ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:41:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:41:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
41 | $assertfailon(a); 41 | $assertfailon(a);
| ^~~~~~~~~~~~~ | ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:42:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:42:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
42 | $assertfailon(a, t); 42 | $assertfailon(a, t);
| ^~~~~~~~~~~~~ | ^~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:44:7: Unsupported: $assertcontrol control_type '9' %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:44:5: Unsupported: $assertcontrol control_type '9'
44 | $assertcontrol(FailOff); 44 | $assertcontrol(FailOff);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:45:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:45:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
45 | $assertfailoff; 45 | $assertfailoff;
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:46:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:46:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
46 | $assertfailoff(a); 46 | $assertfailoff(a);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:47:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:47:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
47 | $assertfailoff(a, t); 47 | $assertfailoff(a, t);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:49:7: Unsupported: $assertcontrol control_type '10' %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:49:5: Unsupported: $assertcontrol control_type '10'
49 | $assertcontrol(NonvacuousOn); 49 | $assertcontrol(NonvacuousOn);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:50:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:50:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
50 | $assertnonvacuouson; 50 | $assertnonvacuouson;
| ^~~~~~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:51:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:51:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
51 | $assertnonvacuouson(a); 51 | $assertnonvacuouson(a);
| ^~~~~~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:52:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:52:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
52 | $assertnonvacuouson(a, t); 52 | $assertnonvacuouson(a, t);
| ^~~~~~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:54:7: Unsupported: $assertcontrol control_type '11' %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:54:5: Unsupported: $assertcontrol control_type '11'
54 | $assertcontrol(VacuousOff); 54 | $assertcontrol(VacuousOff);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:55:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:55:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
55 | $assertvacuousoff; 55 | $assertvacuousoff;
| ^~~~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:56:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:56:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
56 | $assertvacuousoff(a); 56 | $assertvacuousoff(a);
| ^~~~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:57:7: Unsupported: assert control assertion_type %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:57:5: Unsupported: assert control assertion_type
: ... note: In instance 't.unsupported_ctl_type' : ... note: In instance 't.unsupported_ctl_type'
57 | $assertvacuousoff(a, t); 57 | $assertvacuousoff(a, t);
| ^~~~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:64:7: Unsupported: non-const assert control type expression %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:64:5: Unsupported: non-const assert control type expression
: ... note: In instance 't.unsupported_ctl_type_expr' : ... note: In instance 't.unsupported_ctl_type_expr'
64 | $assertcontrol(ctl_type); 64 | $assertcontrol(ctl_type);
| ^~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:93:10: Unsupported: assertcontrols in classes or interfaces %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:93:7: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_class' : ... note: In instance 't.assert_class'
93 | $asserton; 93 | $asserton;
| ^~~~~~~~~ | ^~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:99:10: Unsupported: assertcontrols in classes or interfaces %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:99:7: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_class' : ... note: In instance 't.assert_class'
99 | $assertoff; 99 | $assertoff;
| ^~~~~~~~~~ | ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:172:7: Unsupported: assertcontrols in classes or interfaces %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:172:5: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface' : ... note: In instance 't.assert_iface'
172 | $assertoff; 172 | $assertoff;
| ^~~~~~~~~~ | ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:138:7: Unsupported: assertcontrols in classes or interfaces %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:138:5: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface_class' : ... note: In instance 't.assert_iface_class'
138 | $assertoff; 138 | $assertoff;
| ^~~~~~~~~~ | ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:145:7: Unsupported: assertcontrols in classes or interfaces %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:145:5: Unsupported: assertcontrols in classes or interfaces
: ... note: In instance 't.assert_iface_class' : ... note: In instance 't.assert_iface_class'
145 | $asserton; 145 | $asserton;
| ^~~~~~~~~ | ^~~~~~~~~

4
test_regress/t/t_assert_disable_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_assert_disable_bad.v:27:38: disable iff expression before property call and in its body is not legal %Error: t/t_assert_disable_bad.v:25:37: disable iff expression before property call and in its body is not legal
: ... note: In instance 't' : ... note: In instance 't'
27 | assert property (disable iff (val == 0) check(1, 1)); 25 | assert property (disable iff (val == 0) check(1, 1));
| ^~ | ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to %Error: Exiting due to

8
test_regress/t/t_assert_disable_bad.v
View File

@ -4,12 +4,10 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
int cyc = 0; int cyc = 0;
logic val = 0; logic val = 0;

25
test_regress/t/t_assert_disable_count.v
View File

@ -4,15 +4,14 @@
// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-FileCopyrightText: 2024 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
int cyc; int cyc;
@ -22,28 +21,32 @@ module t (/*AUTOARG*/
int a_false; int a_false;
always @(posedge clk iff !cyc[0]) begin always @(posedge clk iff !cyc[0]) begin
if (cyc < 4 || cyc > 9) ; if (cyc < 4 || cyc > 9);
else a_false = a_false + 1; else a_false = a_false + 1;
end end
int a0_false; int a0_false;
a0: assert property (@(posedge clk) disable iff (cyc[0]) (cyc < 4 || cyc > 9)) a0 :
assert property (@(posedge clk) disable iff (cyc[0]) (cyc < 4 || cyc > 9))
else a0_false = a0_false + 1; else a0_false = a0_false + 1;
int a1_false; int a1_false;
// Note that Verilator supports $inferred_disable in general expression locations // Note that Verilator supports $inferred_disable in general expression locations
// This is a superset of what IEEE specifies // This is a superset of what IEEE specifies
a1: assert property (@(posedge clk) disable iff ($inferred_disable) (cyc < 4 || cyc > 9)) a1 :
assert property (@(posedge clk) disable iff ($inferred_disable) (cyc < 4 || cyc > 9))
else a1_false = a1_false + 1; else a1_false = a1_false + 1;
int a2_false; int a2_false;
// Implicitly uses $inferred_disable // Implicitly uses $inferred_disable
a2: assert property (@(posedge clk) (cyc < 4 || cyc > 9)) a2 :
assert property (@(posedge clk) (cyc < 4 || cyc > 9))
else a2_false = a2_false + 1; else a2_false = a2_false + 1;
int a3_false; int a3_false;
// A different disable iff expression // A different disable iff expression
a3: assert property (@(posedge clk) disable iff (cyc == 5) (cyc < 4 || cyc > 9)) a3 :
assert property (@(posedge clk) disable iff (cyc == 5) (cyc < 4 || cyc > 9))
else a3_false = a3_false + 1; else a3_false = a3_false + 1;
always @(posedge clk) begin always @(posedge clk) begin

8
test_regress/t/t_assert_dup_bad.out
View File

@ -1,8 +1,8 @@
%Error: t/t_assert_dup_bad.v:17:4: Duplicate declaration of block: 'covlabel' %Error: t/t_assert_dup_bad.v:15:3: Duplicate declaration of block: 'covlabel'
17 | covlabel: 15 | covlabel :
| ^~~~~~~~ | ^~~~~~~~
t/t_assert_dup_bad.v:15:4: ... Location of original declaration t/t_assert_dup_bad.v:13:3: ... Location of original declaration
15 | covlabel: 13 | covlabel :
| ^~~~~~~~ | ^~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to %Error: Exiting due to

18
test_regress/t/t_assert_dup_bad.v
View File

@ -4,17 +4,15 @@
// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-FileCopyrightText: 2007 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk; int cyc;
integer cyc = 0;
covlabel: covlabel :
cover property (@(posedge clk) cyc==5); cover property (@(posedge clk) cyc == 5);
covlabel: // Error: Duplicate block_identifier covlabel : // Error: Duplicate block_identifier
cover property (@(posedge clk) cyc==5); cover property (@(posedge clk) cyc == 5);
endmodule endmodule

3
test_regress/t/t_assert_elab.v
View File

@ -8,8 +8,7 @@ module t;
localparam STR = "string"; localparam STR = "string";
function logic checkParameter(input logic [8:0] N); function logic checkParameter(input logic [8:0] N);
$info("For %m, x is %d.", N); $info("For %m, x is %d.", N);
if (N == 1) if (N == 1) return 0;
return 0;
$fatal(1, "Parameter %d is invalid...%s and %s", N, STR, "constant both work"); $fatal(1, "Parameter %d is invalid...%s and %s", N, STR, "constant both work");
endfunction endfunction

50
test_regress/t/t_assert_iff.v
View File

@ -4,21 +4,24 @@
// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-FileCopyrightText: 2023 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk; logic [3:0] enable;
logic[3:0] enable;
int cyc = 0; int cyc = 0;
Test test(.*); Test test (.*);
always @ (posedge clk) begin always @(posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
`ifdef FAIL1 enable[0] <= 1; `endif `ifdef FAIL1
enable[0] <= 1;
`endif
enable[1] <= 1; enable[1] <= 1;
`ifdef FAIL2 enable[2] <= 1; `endif `ifdef FAIL2
enable[2] <= 1;
`endif
enable[3] <= 1; enable[3] <= 1;
if (cyc != 0) begin if (cyc != 0) begin
if (cyc == 10) begin if (cyc == 10) begin
@ -29,29 +32,18 @@ module t (/*AUTOARG*/
end end
endmodule endmodule
module Test( module Test (
input clk, input clk,
input[3:0] enable input [3:0] enable
); );
assert property ( assert property (@(posedge clk iff enable[0]) 0)
@(posedge clk iff enable[0]) else $stop;
0
) else $stop;
assert property ( assert property (@(posedge clk iff enable[1]) 1);
@(posedge clk iff enable[1])
1
);
cover property ( cover property (@(posedge clk iff enable[2]) 1) $stop;
@(posedge clk iff enable[2])
1
) $stop;
cover property ( cover property (@(posedge clk iff enable[3]) 0) $stop;
@(posedge clk iff enable[3])
0
) $stop;
endmodule endmodule

2
test_regress/t/t_assert_iff_clk_unsup.out
View File

@ -1,4 +1,4 @@
%Error-UNSUPPORTED: t/t_assert_iff_clk_unsup.v:20:21: Unsupported: property '(disable iff (...) @ (...)' %Error-UNSUPPORTED: t/t_assert_iff_clk_unsup.v:20:20: Unsupported: property '(disable iff (...) @ (...)'
: ... Suggest use property '(@(...) disable iff (...))' : ... Suggest use property '(@(...) disable iff (...))'
20 | assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5); 20 | assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5);
| ^~~~~~~ | ^~~~~~~

6
test_regress/t/t_assert_iff_clk_unsup.v
View File

@ -4,9 +4,9 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
clk input clk
); );
input clk; input clk;
int cyc = 0; int cyc = 0;

4
test_regress/t/t_assert_imm_nz_bad.out
View File

@ -1,5 +1,5 @@
%Error: t/t_assert_imm_nz_bad.v:13:26: Deferred assertions must use '#0' (IEEE 1800-2023 16.4) %Error: t/t_assert_imm_nz_bad.v:14:11: Deferred assertions must use '#0' (IEEE 1800-2023 16.4)
13 | labeled_imas: assert #1 (clk); 14 | assert #1 (clk);
| ^ | ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to %Error: Exiting due to

9
test_regress/t/t_assert_imm_nz_bad.v
View File

@ -4,12 +4,13 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
clk input clk
); );
input clk; input clk;
labeled_imas: assert #1 (clk); // BAD: #1 labeled_imas :
assert #1 (clk); // BAD: #1
endmodule endmodule

113
test_regress/t/t_assert_implication.v
View File

@ -4,26 +4,26 @@
// SPDX-FileCopyrightText: 2019 Peter Monsson // SPDX-FileCopyrightText: 2019 Peter Monsson
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk; integer cyc;
integer cyc; initial cyc=1; initial cyc = 1;
Test test (/*AUTOINST*/ Test test ( /*AUTOINST*/
// Inputs // Inputs
.clk(clk), .clk(clk),
.cyc(cyc)); .cyc(cyc)
);
always @ (posedge clk) begin always @(posedge clk) begin
if (cyc!=0) begin if (cyc != 0) begin
cyc <= cyc + 1; cyc <= cyc + 1;
`ifdef TEST_VERBOSE `ifdef TEST_VERBOSE
$display("cyc=%0d", cyc); $display("cyc=%0d", cyc);
`endif `endif
if (cyc==10) begin if (cyc == 10) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
@ -32,99 +32,56 @@ module t (/*AUTOARG*/
endmodule endmodule
module Test module Test (
(
input clk, input clk,
input integer cyc input integer cyc
); );
`ifdef FAIL_ASSERT_1 `ifdef FAIL_ASSERT_1
assert property ( assert property (@(posedge clk) 1 |-> 0)
@(posedge clk) else $display("[%0t] wrong implication", $time);
1 |-> 0
) else $display("[%0t] wrong implication", $time);
assert property ( assert property (@(posedge clk) 1 |=> 0)
@(posedge clk) else $display("[%0t] wrong implication", $time);
1 |=> 0
) else $display("[%0t] wrong implication", $time);
assert property ( assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 1)
@(posedge clk) else $display("[%0t] wrong implication (step)", $time);
cyc%3==1 |=> cyc%3==1
) else $display("[%0t] wrong implication (step)", $time);
assert property ( assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 0)
@(posedge clk) else $display("[%0t] wrong implication (step)", $time);
cyc%3==1 |=> cyc%3==0
) else $display("[%0t] wrong implication (step)", $time);
assert property ( assert property (@(posedge clk) disable iff (cyc == 3) (cyc == 4) |=> 0)
@(posedge clk) disable iff (cyc == 3) else $display("[%0t] wrong implication (disable)", $time);
(cyc == 4) |=> 0
) else $display("[%0t] wrong implication (disable)", $time);
assert property ( assert property (@(posedge clk) disable iff (cyc == 6) (cyc == 4) |=> 0)
@(posedge clk) disable iff (cyc == 6) else $display("[%0t] wrong implication (disable)", $time);
(cyc == 4) |=> 0
) else $display("[%0t] wrong implication (disable)", $time);
`endif `endif
// Test |-> // Test |->
assert property ( assert property (@(posedge clk) 1 |-> 1);
@(posedge clk)
1 |-> 1
);
assert property ( assert property (@(posedge clk) 0 |-> 0);
@(posedge clk)
0 |-> 0
);
assert property ( assert property (@(posedge clk) 0 |-> 1);
@(posedge clk)
0 |-> 1
);
// Test |=> // Test |=>
assert property ( assert property (@(posedge clk) 1 |=> 1);
@(posedge clk)
1 |=> 1
);
assert property ( assert property (@(posedge clk) 0 |=> 0);
@(posedge clk)
0 |=> 0
);
assert property ( assert property (@(posedge clk) 0 |=> 1);
@(posedge clk)
0 |=> 1
);
// Test correct handling of time step in |=> // Test correct handling of time step in |=>
assert property ( assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 2);
@(posedge clk)
cyc%3==1 |=> cyc%3==2
);
// Test correct handling of disable iff // Test correct handling of disable iff
assert property ( assert property (@(posedge clk) disable iff ($sampled(cyc) < 3) 1 |=> cyc > 3);
@(posedge clk) disable iff ($sampled(cyc) < 3)
1 |=> cyc > 3
);
// Test correct handling of disable iff in current cycle // Test correct handling of disable iff in current cycle
assert property ( assert property (@(posedge clk) disable iff ($sampled(cyc) == 4) (cyc == 4) |=> 0);
@(posedge clk) disable iff ($sampled(cyc) == 4)
(cyc == 4) |=> 0
);
// Test correct handling of disable iff in previous cycle // Test correct handling of disable iff in previous cycle
assert property ( assert property (@(posedge clk) disable iff (cyc == 5) (cyc == 4) |=> 0);
@(posedge clk) disable iff (cyc == 5)
(cyc == 4) |=> 0
);
endmodule endmodule

11
test_regress/t/t_assert_on.v
View File

@ -4,14 +4,11 @@
// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-FileCopyrightText: 2007 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk; always @(posedge clk) begin
always @ (posedge clk) begin
assert (0); assert (0);
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;

11
test_regress/t/t_assert_past.v
View File

@ -4,10 +4,9 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
clk input clk
); );
input clk;
int cyc = 0; int cyc = 0;
logic val = 0; logic val = 0;
// Example: // Example:
@ -20,9 +19,9 @@ module t (/*AUTOARG*/
$finish; $finish;
end end
end end
assert property(@(posedge clk) cyc % 2 == 0 |=> $past(val) == 0) assert property (@(posedge clk) cyc % 2 == 0 |=> $past(val) == 0)
else $display("$past assert 1 failed"); else $display("$past assert 1 failed");
assert property(@(posedge clk) cyc % 2 == 1 |=> $past(val) == 1) assert property (@(posedge clk) cyc % 2 == 1 |=> $past(val) == 1)
else $display("$past assert 2 failed"); else $display("$past assert 2 failed");
// Example end // Example end
endmodule endmodule

8
test_regress/t/t_assert_procedural_clk_bad.out
View File

@ -1,10 +1,10 @@
%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:21:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) %Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:19:9: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
: ... note: In instance 't' : ... note: In instance 't'
21 | assume property (@(posedge clk) cyc == 9); 19 | assume property (@(posedge clk) cyc == 9);
| ^~~~~~ | ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:22:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) %Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:20:9: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
: ... note: In instance 't' : ... note: In instance 't'
22 | assume property (@(negedge clk) cyc == 9); 20 | assume property (@(negedge clk) cyc == 9);
| ^~~~~~ | ^~~~~~
%Error: Exiting due to %Error: Exiting due to

20
test_regress/t/t_assert_procedural_clk_bad.v
View File

@ -4,24 +4,22 @@
// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-FileCopyrightText: 2023 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk; integer cyc;
initial cyc = 1;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0]; wire [7:0] cyc_copy = cyc[7:0];
always @ (posedge clk) begin always @(posedge clk) begin
if (cyc!=0) begin if (cyc != 0) begin
cyc <= cyc + 1; cyc <= cyc + 1;
if (cyc==9) begin if (cyc == 9) begin
assume property (@(posedge clk) cyc == 9); assume property (@(posedge clk) cyc == 9);
assume property (@(negedge clk) cyc == 9); assume property (@(negedge clk) cyc == 9);
end end
if (cyc==10) begin if (cyc == 10) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end

68
test_regress/t/t_assert_sampled.v
View File

@ -4,20 +4,32 @@
// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-FileCopyrightText: 2022 Antmicro Ltd
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
reg [3:0] a, b; reg [3:0] a, b;
Test1 t1(clk, a, b); Test1 t1 (
Test2 t2(clk, a, b); clk,
Test3 t3(clk, a, b); a,
b
);
Test2 t2 (
clk,
a,
b
);
Test3 t3 (
clk,
a,
b
);
initial begin initial begin
a = 0; a = 0;
@ -37,9 +49,11 @@ module t (/*AUTOARG*/
end end
endmodule endmodule
module Test1( module Test1 (
clk, a, b clk,
); a,
b
);
input clk; input clk;
input [3:0] a, b; input [3:0] a, b;
@ -48,9 +62,11 @@ module Test1(
endmodule endmodule
module Test2( module Test2 (
clk, a, b clk,
); a,
b
);
input clk; input clk;
input [3:0] a, b; input [3:0] a, b;
@ -59,22 +75,28 @@ module Test2(
endmodule endmodule
module Test3( module Test3 (
clk, a, b clk,
); a,
b
);
input clk; input clk;
input [3:0] a, b; input [3:0] a, b;
int hits[10]; int hits[10];
assert property (@(posedge clk) a == b) hits[1]=1; assert property (@(posedge clk) a == b) hits[1] = 1;
assert property (@(posedge clk) a == b) else hits[2]=1; assert property (@(posedge clk) a == b)
assert property (@(posedge clk) a == b) hits[3]=1; else hits[4]=1; else hits[2] = 1;
assert property (@(posedge clk) a == b) hits[3] = 1;
else hits[4] = 1;
assert property (@(posedge clk) a != b) hits[5]=1; assert property (@(posedge clk) a != b) hits[5] = 1;
assert property (@(posedge clk) a != b) else hits[6]=1; assert property (@(posedge clk) a != b)
assert property (@(posedge clk) a != b) hits[7]=1; else hits[8]=1; else hits[6] = 1;
assert property (@(posedge clk) a != b) hits[7] = 1;
else hits[8] = 1;
final begin final begin
`checkd(hits[1], 1); `checkd(hits[1], 1);

9
test_regress/t/t_assert_synth.v
View File

@ -4,12 +4,9 @@
// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-FileCopyrightText: 2005 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
reg a; initial a = 1'b1; reg a; initial a = 1'b1;
reg b_fc; initial b_fc = 1'b0; reg b_fc; initial b_fc = 1'b0;

10
test_regress/t/t_assert_synth_full.out
View File

@ -1,6 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test [0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test [0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test [0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found for '2'h3' [40] %Error: t_assert_synth.v:28: Assertion failed in top.t: synthesis full_case, but non-match found for '2'h3'
%Error: t/t_assert_synth.v:31: Verilog $stop %Error: t/t_assert_synth.v:28: Verilog $stop
Aborting... Aborting...

10
test_regress/t/t_assert_synth_full_vlt.out
View File

@ -1,6 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test [0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test [0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test [0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:40: Assertion failed in top.t: priority case, but non-match found for '2'h3' [40] %Error: t_assert_synth.v:37: Assertion failed in top.t: priority case, but non-match found for '2'h3'
%Error: t/t_assert_synth.v:40: Verilog $stop %Error: t/t_assert_synth.v:37: Verilog $stop
Aborting... Aborting...

10
test_regress/t/t_assert_synth_parallel.out
View File

@ -1,6 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test [0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test [0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test [0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:50: Assertion failed in top.t: synthesis full_case parallel_case, but multiple matches found for '1'h1' [40] %Error: t_assert_synth.v:47: Assertion failed in top.t: synthesis full_case parallel_case, but multiple matches found for '1'h1'
%Error: t/t_assert_synth.v:50: Verilog $stop %Error: t/t_assert_synth.v:47: Verilog $stop
Aborting... Aborting...

2
test_regress/t/t_assert_synth_parallel.vlt
View File

@ -6,4 +6,4 @@
`verilator_config `verilator_config
parallel_case -file "t/t_assert_synth.v" -lines 55 parallel_case -file "t/t_assert_synth.v" -lines 52

10
test_regress/t/t_assert_synth_parallel_vlt.out
View File

@ -1,6 +1,6 @@
[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test [0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test [0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test [0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:55: Assertion failed in top.t: synthesis parallel_case, but multiple matches found for '1'h1' [40] %Error: t_assert_synth.v:52: Assertion failed in top.t: synthesis parallel_case, but multiple matches found for '1'h1'
%Error: t/t_assert_synth.v:55: Verilog $stop %Error: t/t_assert_synth.v:52: Verilog $stop
Aborting... Aborting...

10
test_regress/t/t_assert_unique_case_bad.v
View File

@ -4,12 +4,12 @@
// SPDX-FileCopyrightText: 2024 Yutetsu TAKATSUKASA // SPDX-FileCopyrightText: 2024 Yutetsu TAKATSUKASA
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t ( /*AUTOARG*/
// Outputs // Outputs
hit, hit,
// Inputs // Inputs
clk clk
); );
input clk; input clk;
output logic hit; output logic hit;
@ -21,11 +21,11 @@ module t (/*AUTOARG*/
initial addr = 32'h380; initial addr = 32'h380;
always @ (posedge clk) begin always @(posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
addr <= 32'h380 + cyc; addr <= 32'h380 + cyc;
match_item0 = 12'h 380 + cyc[11:0]; match_item0 = 12'h380 + cyc[11:0];
match_item1 = 12'h 390 - cyc[11:0]; match_item1 = 12'h390 - cyc[11:0];
$sformat(s, "%1d", cyc); $sformat(s, "%1d", cyc);
if (cyc == 9) begin if (cyc == 9) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");

46
test_regress/t/t_assign_expr.v
View File

@ -4,8 +4,10 @@
// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-FileCopyrightText: 2022 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t; module t;
@ -17,60 +19,76 @@ module t;
initial begin initial begin
a = 10; a = 10;
i = (a = 2); i = (a = 2);
`checkd(a, 2); `checkd(i, 2); `checkd(a, 2);
`checkd(i, 2);
a = 10; a = 10;
i = (a += 2); i = (a += 2);
`checkd(a, 12); `checkd(i, 12); `checkd(a, 12);
`checkd(i, 12);
a = 10; a = 10;
i = (a -= 2); i = (a -= 2);
`checkd(a, 8); `checkd(i, 8); `checkd(a, 8);
`checkd(i, 8);
a = 10; a = 10;
i = (a *= 2); i = (a *= 2);
`checkd(a, 20); `checkd(i, 20); `checkd(a, 20);
`checkd(i, 20);
a = 10; a = 10;
i = (a /= 2); i = (a /= 2);
`checkd(a, 5); `checkd(i, 5); `checkd(a, 5);
`checkd(i, 5);
a = 11; a = 11;
i = (a %= 2); i = (a %= 2);
`checkd(a, 1); `checkd(i, 1); `checkd(a, 1);
`checkd(i, 1);
a = 10; a = 10;
i = (a &= 2); i = (a &= 2);
`checkd(a, 2); `checkd(i, 2); `checkd(a, 2);
`checkd(i, 2);
a = 8; a = 8;
i = (a |= 2); i = (a |= 2);
`checkd(a, 10); `checkd(i, 10); `checkd(a, 10);
`checkd(i, 10);
a = 10; a = 10;
i = (a ^= 2); i = (a ^= 2);
`checkd(a, 8); `checkd(i, 8); `checkd(a, 8);
`checkd(i, 8);
a = 10; a = 10;
i = (a <<= 2); i = (a <<= 2);
`checkd(a, 40); `checkd(i, 40); `checkd(a, 40);
`checkd(i, 40);
a = 10; a = 10;
i = (a >>= 2); i = (a >>= 2);
`checkd(a, 2); `checkd(i, 2); `checkd(a, 2);
`checkd(i, 2);
a = 10; a = 10;
i = (a >>>= 2); i = (a >>>= 2);
`checkd(a, 2); `checkd(i, 2); `checkd(a, 2);
`checkd(i, 2);
a = 10; a = 10;
i = (a = (b = 5)); i = (a = (b = 5));
`checkd(a, 5); `checkd(i, 5); `checkd(b, 5); `checkd(a, 5);
`checkd(i, 5);
`checkd(b, 5);
a = 10; a = 10;
b = 6; b = 6;
i = ((a += (b += 1) + 1)); i = ((a += (b += 1) + 1));
`checkd(a, 18); `checkd(i, 18); `checkd(b, 7); `checkd(a, 18);
`checkd(i, 18);
`checkd(b, 7);
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;

18
test_regress/t/t_assign_inline.v
View File

@ -4,13 +4,11 @@
// SPDX-FileCopyrightText: 2015 Mike Thyer // SPDX-FileCopyrightText: 2015 Mike Thyer
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
int cycle=0; int cycle = 0;
// verilator lint_off UNOPTFLAT // verilator lint_off UNOPTFLAT
reg [7:0] a_r; reg [7:0] a_r;
@ -29,18 +27,18 @@ module t (/*AUTOARG*/
// stimulus + checks // stimulus + checks
always @(posedge clk) begin always @(posedge clk) begin
cycle <= cycle+1; cycle <= cycle + 1;
if (cycle==0) begin if (cycle == 0) begin
c_q_r <= 8'b0; c_q_r <= 8'b0;
end end
else begin else begin
c_q_r <= c_d_r+1; c_q_r <= c_d_r + 1;
`ifdef TEST_VERBOSE `ifdef TEST_VERBOSE
$display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same $display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same
`endif `endif
end end
if (cycle >= 10) begin if (cycle >= 10) begin
if (b_r==9) begin if (b_r == 9) begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end

47
test_regress/t/t_assign_slice_overflow.v
View File

@ -23,11 +23,9 @@
// SPDX-FileCopyrightText: 2021 David Turner // SPDX-FileCopyrightText: 2021 David Turner
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
integer cyc = 0; integer cyc = 0;
// Non-constant offsets // Non-constant offsets
@ -59,86 +57,88 @@ module t(/*AUTOARG*/
always @(*) begin always @(*) begin
// Non-constant select offset, destination narrow // Non-constant select offset, destination narrow
dstnarrow = 2'd0; dstnarrow = 2'd0;
dstnarrow[varoffset1 +: 2'd2] = 2'd2; dstnarrow[varoffset1+:2'd2] = 2'd2;
// Non-constant select offset, destination wide, width == 1 // Non-constant select offset, destination wide, width == 1
dstwide1 = 70'd0; dstwide1 = 70'd0;
dstwide1[varoffset2 +: 1'd1] = 1'd1; dstwide1[varoffset2+:1'd1] = 1'd1;
// Non-constant select offset, destination wide, width != 1 // Non-constant select offset, destination wide, width != 1
dstwide2 = 70'd0; dstwide2 = 70'd0;
dstwide2[varoffset3 +: 2'd2] = 2'd2; dstwide2[varoffset3+:2'd2] = 2'd2;
// Constant offset, IData into CData // Constant offset, IData into CData
constoffset = 7'd2; constoffset = 7'd2;
dst_cdata = 3'd0; dst_cdata = 3'd0;
dst_cdata[constoffset[0 +: 2] +: 3'd3] = 3'd6; dst_cdata[constoffset[0+:2]+:3'd3] = 3'd6;
// Constant offset, IData into SData // Constant offset, IData into SData
constoffset = 7'd11; constoffset = 7'd11;
dst_sdata = 12'd0; dst_sdata = 12'd0;
dst_sdata[constoffset[0 +: 4] +: 2'd2] = 2'd2; dst_sdata[constoffset[0+:4]+:2'd2] = 2'd2;
// Constant offset, IData into IData // Constant offset, IData into IData
constoffset = 7'd29; constoffset = 7'd29;
dst_idata = 30'd0; dst_idata = 30'd0;
dst_idata[constoffset[0 +: 5] +: 2'd2] = 2'd2; dst_idata[constoffset[0+:5]+:2'd2] = 2'd2;
// Constant offset, QData into QData // Constant offset, QData into QData
constoffset = 7'd59; constoffset = 7'd59;
dst_qdata = 60'd0; dst_qdata = 60'd0;
dst_qdata[constoffset[0 +: 6] +: 2'd2] = 2'd2; dst_qdata[constoffset[0+:6]+:2'd2] = 2'd2;
// Constant offset, IData into WData within word // Constant offset, IData into WData within word
constoffset = 7'd69; constoffset = 7'd69;
dst_wdata1 = 70'd0; dst_wdata1 = 70'd0;
dst_wdata1[constoffset +: 2'd2] = 2'd2; dst_wdata1[constoffset+:2'd2] = 2'd2;
// Constant offset, IData into WData crossing word boundary // Constant offset, IData into WData crossing word boundary
constoffset = 7'd61; constoffset = 7'd61;
dst_wdata2 = 70'd0; dst_wdata2 = 70'd0;
dst_wdata2[constoffset +: 4'd10] = 10'd1 << 4'd9; dst_wdata2[constoffset+:4'd10] = 10'd1 << 4'd9;
// Constant offset, IData into WData replacing a whole word // Constant offset, IData into WData replacing a whole word
constoffset = 7'd64; constoffset = 7'd64;
dst_wdata3 = 70'd0; dst_wdata3 = 70'd0;
dst_wdata3[constoffset +: 6'd32] = 32'd1 << 3'd6; dst_wdata3[constoffset+:6'd32] = 32'd1 << 3'd6;
// Constant offset, QData into WData // Constant offset, QData into WData
constoffset = 7'd31; constoffset = 7'd31;
dst_wdata4 = 70'd0; dst_wdata4 = 70'd0;
dst_wdata4[constoffset +: 7'd40] = 40'd1 << 7'd39; dst_wdata4[constoffset+:7'd40] = 40'd1 << 7'd39;
// Constant offset, WData into WData replacing whole words // Constant offset, WData into WData replacing whole words
constoffset = 7'd32; constoffset = 7'd32;
dst_wdata5 = 70'd0; dst_wdata5 = 70'd0;
dst_wdata5[constoffset +: 7'd64] = 64'd1 << 7'd38; dst_wdata5[constoffset+:7'd64] = 64'd1 << 7'd38;
// Constant offset, WData into WData offset word aligned // Constant offset, WData into WData offset word aligned
constoffset = 7'd32; constoffset = 7'd32;
dst_wdata6 = 70'd0; dst_wdata6 = 70'd0;
dst_wdata6[constoffset +: 7'd40] = 40'd1 << 7'd38; dst_wdata6[constoffset+:7'd40] = 40'd1 << 7'd38;
// Constant offset, WData into WData unaligned // Constant offset, WData into WData unaligned
constoffset = 7'd1; constoffset = 7'd1;
dst_wdata7 = 70'd0; dst_wdata7 = 70'd0;
dst_wdata7[constoffset +: 7'd70] = 70'd1 << 7'd69; dst_wdata7[constoffset+:7'd70] = 70'd1 << 7'd69;
end end
// Test loop // Test loop
always @ (posedge clk) begin always @(posedge clk) begin
// State machine to avoid verilator constant-folding offset // State machine to avoid verilator constant-folding offset
if (cyc == 0) begin if (cyc == 0) begin
// Initialisation // Initialisation
varoffset1 <= 1'd0; varoffset1 <= 1'd0;
varoffset2 <= 7'd0; varoffset2 <= 7'd0;
varoffset3 <= 7'd0; varoffset3 <= 7'd0;
end else if (cyc == 1) begin end
else if (cyc == 1) begin
// Variable offsets set here to avoid verilator constant folding // Variable offsets set here to avoid verilator constant folding
varoffset1 <= 1'd1; varoffset1 <= 1'd1;
varoffset2 <= 7'd70; varoffset2 <= 7'd70;
varoffset3 <= 7'd69; varoffset3 <= 7'd69;
end else if (cyc == 2) begin end
else if (cyc == 2) begin
// Check all destinations are 0 // Check all destinations are 0
$write("dstwide1 = %23d, downshifted = %23d\n", dstwide1, dstwide1 >> 1); $write("dstwide1 = %23d, downshifted = %23d\n", dstwide1, dstwide1 >> 1);
$write("dstwide2 = %23d, downshifted = %23d\n", dstwide2, dstwide2 >> 1); $write("dstwide2 = %23d, downshifted = %23d\n", dstwide2, dstwide2 >> 1);
@ -169,7 +169,8 @@ module t(/*AUTOARG*/
if (dst_wdata5 !== 70'd0 || (dst_wdata5 >> 1) !== 70'd0) $stop; if (dst_wdata5 !== 70'd0 || (dst_wdata5 >> 1) !== 70'd0) $stop;
if (dst_wdata6 !== 70'd0 || (dst_wdata6 >> 1) !== 70'd0) $stop; if (dst_wdata6 !== 70'd0 || (dst_wdata6 >> 1) !== 70'd0) $stop;
if (dst_wdata7 !== 70'd0 || (dst_wdata7 >> 1) !== 70'd0) $stop; if (dst_wdata7 !== 70'd0 || (dst_wdata7 >> 1) !== 70'd0) $stop;
end else begin end
else begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end

2
test_regress/t/t_assigndly_dynamic_notiming_bad.out
View File

@ -1,4 +1,4 @@
%Error-NOTIMING: t/t_assigndly_dynamic_notiming_bad.v:10:11: Delayed assignment in a non-inlined function/task requires --timing %Error-NOTIMING: t/t_assigndly_dynamic_notiming_bad.v:10:9: Delayed assignment in a non-inlined function/task requires --timing
: ... note: In instance '$unit::Cls' : ... note: In instance '$unit::Cls'
10 | qux <= '1; 10 | qux <= '1;
| ^~ | ^~

157
test_regress/t/t_assoc.v
View File

@ -4,116 +4,163 @@
// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
// verilog_format: on
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
integer cyc = 0; integer cyc = 0;
integer i; integer i;
always @ (posedge clk) begin always @(posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
begin begin
// Type // Type
typedef bit [3:0] nibble_t; typedef bit [3:0] nibble_t;
typedef string dict_t [nibble_t]; typedef string dict_t[nibble_t];
dict_t a; dict_t a;
string b [nibble_t]; string b[nibble_t];
nibble_t k; nibble_t k;
string v; string v;
a[4'd3] = "fooed"; a[4'd3] = "fooed";
a[4'd2] = "bared"; a[4'd2] = "bared";
i = a.num(); `checkh(i, 2); i = a.num();
i = a.size; `checkh(i, 2); // Also checks no parens `checkh(i, 2);
v = a[4'd3]; `checks(v, "fooed"); i = a.size;
v = a[4'd2]; `checks(v, "bared"); `checkh(i, 2); // Also checks no parens
i = a.exists(4'd0); `checkh(i, 0); v = a[4'd3];
`checks(v, "fooed");
v = a[4'd2];
`checks(v, "bared");
i = a.exists(4'd0);
`checkh(i, 0);
if (a.exists(4'd0)) $stop; // Check no width warning if (a.exists(4'd0)) $stop; // Check no width warning
i = a.exists(4'd2); `checkh(i, 1); i = a.exists(4'd2);
`checkh(i, 1);
if (!a.exists(4'd2)) $stop; // Check no width warning if (!a.exists(4'd2)) $stop; // Check no width warning
i = a.first(k); `checkh(i, 1); `checks(k, 4'd2); i = a.first(k);
i = a.next(k); `checkh(i, 1); `checks(k, 4'd3); `checkh(i, 1);
i = a.next(k); `checkh(i, 0); `checks(k, 4'd2);
i = a.last(k); `checkh(i, 1); `checks(k, 4'd3); i = a.next(k);
i = a.prev(k); `checkh(i, 1); `checks(k, 4'd2); `checkh(i, 1);
i = a.prev(k); `checkh(i, 0); `checks(k, 4'd3);
i = a.next(k);
`checkh(i, 0);
i = a.last(k);
`checkh(i, 1);
`checks(k, 4'd3);
i = a.prev(k);
`checkh(i, 1);
`checks(k, 4'd2);
i = a.prev(k);
`checkh(i, 0);
`checkp(a, "'{'h2:\"bared\", 'h3:\"fooed\"}"); `checkp(a, "'{'h2:\"bared\", 'h3:\"fooed\"}");
a.first(k); `checks(k, 4'd2); a.first(k);
a.next(k); `checks(k, 4'd3); `checks(k, 4'd2);
a.next(k); a.next(k);
a.last(k); `checks(k, 4'd3); `checks(k, 4'd3);
a.prev(k); `checks(k, 4'd2); a.next(k);
a.last(k);
`checks(k, 4'd3);
a.prev(k);
`checks(k, 4'd2);
a.delete(4'd2); a.delete(4'd2);
i = a.size(); `checkh(i, 1); i = a.size();
`checkh(i, 1);
b = a; // Copy assignment b = a; // Copy assignment
i = b.size(); `checkh(i, 1); i = b.size();
`checkh(i, 1);
end end
begin begin
// Strings // Strings
string a [string]; string a[string];
string k; string k;
string v; string v;
a["foo"] = "fooed"; a["foo"] = "fooed";
a["bar"] = "bared"; a["bar"] = "bared";
i = a.num(); `checkh(i, 2); i = a.num();
i = a.size(); `checkh(i, 2); `checkh(i, 2);
v = a["foo"]; `checks(v, "fooed"); i = a.size();
v = a["bar"]; `checks(v, "bared"); `checkh(i, 2);
i = a.exists("baz"); `checkh(i, 0); v = a["foo"];
i = a.exists("bar"); `checkh(i, 1); `checks(v, "fooed");
i = a.first(k); `checkh(i, 1); `checks(k, "bar"); v = a["bar"];
i = a.next(k); `checkh(i, 1); `checks(k, "foo"); `checks(v, "bared");
i = a.next(k); `checkh(i, 0); i = a.exists("baz");
i = a.last(k); `checkh(i, 1); `checks(k, "foo"); `checkh(i, 0);
i = a.prev(k); `checkh(i, 1); `checks(k, "bar"); i = a.exists("bar");
i = a.prev(k); `checkh(i, 0); `checkh(i, 1);
i = a.first(k);
`checkh(i, 1);
`checks(k, "bar");
i = a.next(k);
`checkh(i, 1);
`checks(k, "foo");
i = a.next(k);
`checkh(i, 0);
i = a.last(k);
`checkh(i, 1);
`checks(k, "foo");
i = a.prev(k);
`checkh(i, 1);
`checks(k, "bar");
i = a.prev(k);
`checkh(i, 0);
`checkp(a["foo"], "\"fooed\""); `checkp(a["foo"], "\"fooed\"");
`checkp(a, "'{\"bar\":\"bared\", \"foo\":\"fooed\"}"); `checkp(a, "'{\"bar\":\"bared\", \"foo\":\"fooed\"}");
a.delete("bar"); a.delete("bar");
i = a.size(); `checkh(i, 1); i = a.size();
`checkh(i, 1);
a.delete(); a.delete();
i = a.size(); `checkh(i, 0); i = a.size();
i = a.first(k); `checkh(i, 0); `checkh(i, 0);
i = a.last(k); `checkh(i, 0); i = a.first(k);
`checkh(i, 0);
i = a.last(k);
`checkh(i, 0);
// Patterns & default // Patterns & default
a = '{ "f": "fooed", "b": "bared", default: "defaulted" }; a = '{"f": "fooed", "b": "bared", default: "defaulted"};
i = a.size(); `checkh(i, 2); // Default doesn't count i = a.size();
v = a["f"]; `checks(v, "fooed"); `checkh(i, 2); // Default doesn't count
v = a["b"]; `checks(v, "bared"); v = a["f"];
v = a["NEXISTS"]; `checks(v, "defaulted"); `checks(v, "fooed");
v = a["b"];
`checks(v, "bared");
v = a["NEXISTS"];
`checks(v, "defaulted");
a = '{}; a = '{};
i = a.size(); `checkh(i, 0); i = a.size();
`checkh(i, 0);
end end
begin begin
// Wide-wides - need special array container classes, ick. // Wide-wides - need special array container classes, ick.
logic [91:2] a [ logic [65:1] ]; logic [91:2] a[logic [65:1]];
int b [ bit [99:0] ]; int b[bit [99:0]];
a[~65'hfe] = ~ 90'hfee; a[~65'hfe] = ~90'hfee;
`checkh(a[~65'hfe], ~ 90'hfee); `checkh(a[~65'hfe], ~90'hfee);
b[100'b1] = 1; b[100'b1] = 1;
`checkh(b[100'b1], 1); `checkh(b[100'b1], 1);
end end
begin begin
int a [string]; int a[string];
int sum; int sum;
sum = 0; sum = 0;
a["one"] = 1; a["one"] = 1;
@ -125,7 +172,7 @@ module t (/*AUTOARG*/
begin // Issue #5435 begin // Issue #5435
int a; int a;
int ok; int ok;
int dict [int]; int dict[int];
dict[3] = 'h13; dict[3] = 'h13;
dict[4] = 'h14; dict[4] = 'h14;

14
test_regress/t/t_assoc2.v
View File

@ -4,22 +4,22 @@
// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
integer cyc = 0; integer cyc = 0;
int imap[int]; int imap[int];
// associative array of an associative array // associative array of an associative array
logic [31:0] a [logic [31:0]][logic [63:0]]; logic [31:0] a[logic [31:0]][logic [63:0]];
task static disp(); task static disp();
int i = 60; int i = 60;
@ -28,7 +28,7 @@ module t (/*AUTOARG*/
foreach (imap[k]) $display("imap[%0d] = %0d", k, imap[k]); foreach (imap[k]) $display("imap[%0d] = %0d", k, imap[k]);
endtask endtask
always @ (posedge clk) begin always @(posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
if (cyc == 1) begin if (cyc == 1) begin
a[5][8] = 8; a[5][8] = 8;

4
test_regress/t/t_assoc_compare.v
View File

@ -4,11 +4,13 @@
// SPDX-FileCopyrightText: 2023 Ilya Barkov // SPDX-FileCopyrightText: 2023 Ilya Barkov
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end `define check_comp(lhs, rhs, op, expv) if ((expv) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (expv)); `stop; end
// Two checks because == and != may not be derived from each other // Two checks because == and != may not be derived from each other
`define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0) `define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0)
`define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1) `define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1)
// verilog_format: on
class Cls; class Cls;
int i; int i;

10
test_regress/t/t_assoc_enum.v
View File

@ -12,10 +12,16 @@
class X; class X;
typedef enum int { typedef enum int {
INITIAL, RUNNING, SUSPENDED, COMPLETING, DONE INITIAL,
RUNNING,
SUSPENDED,
COMPLETING,
DONE
} state_t; } state_t;
static string state_names[state_t] = '{ static
string
state_names[state_t] = '{
INITIAL: "INITIAL", INITIAL: "INITIAL",
RUNNING: "RUNNING", RUNNING: "RUNNING",
SUSPENDED: "SUSPENDED", SUSPENDED: "SUSPENDED",

3
test_regress/t/t_assoc_method.v
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@ -4,10 +4,11 @@
// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-FileCopyrightText: 2024 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
// verilog_format: on
module t; module t;
typedef struct {int x, y;} point; typedef struct {int x, y;} point;

32
test_regress/t/t_assoc_method_bad.out
View File

@ -1,66 +1,66 @@
%Error: t/t_assoc_method_bad.v:14:13: The 1 arguments passed to .num method does not match its requiring 0 arguments %Error: t/t_assoc_method_bad.v:14:11: The 1 arguments passed to .num method does not match its requiring 0 arguments
: ... note: In instance 't' : ... note: In instance 't'
14 | v = a.num("badarg"); 14 | v = a.num("badarg");
| ^~~ | ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_assoc_method_bad.v:15:13: The 1 arguments passed to .size method does not match its requiring 0 arguments %Error: t/t_assoc_method_bad.v:15:11: The 1 arguments passed to .size method does not match its requiring 0 arguments
: ... note: In instance 't' : ... note: In instance 't'
15 | v = a.size("badarg"); 15 | v = a.size("badarg");
| ^~~~ | ^~~~
%Error: t/t_assoc_method_bad.v:16:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments %Error: t/t_assoc_method_bad.v:16:11: The 0 arguments passed to .exists method does not match its requiring 1 arguments
: ... note: In instance 't' : ... note: In instance 't'
16 | v = a.exists(); 16 | v = a.exists();
| ^~~~~~ | ^~~~~~
%Error: t/t_assoc_method_bad.v:17:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments %Error: t/t_assoc_method_bad.v:17:11: The 2 arguments passed to .exists method does not match its requiring 1 arguments
: ... note: In instance 't' : ... note: In instance 't'
17 | v = a.exists(k, "bad2"); 17 | v = a.exists(k, "bad2");
| ^~~~~~ | ^~~~~~
%Error: t/t_assoc_method_bad.v:18:13: The 0 arguments passed to .first method does not match its requiring 1 arguments %Error: t/t_assoc_method_bad.v:18:11: The 0 arguments passed to .first method does not match its requiring 1 arguments
: ... note: In instance 't' : ... note: In instance 't'
18 | v = a.first(); 18 | v = a.first();
| ^~~~~ | ^~~~~
%Error-UNSUPPORTED: t/t_assoc_method_bad.v:18:13: Unsupported: Non-variable on LHS of built-in method 'first' %Error-UNSUPPORTED: t/t_assoc_method_bad.v:18:11: Unsupported: Non-variable on LHS of built-in method 'first'
: ... note: In instance 't' : ... note: In instance 't'
18 | v = a.first(); 18 | v = a.first();
| ^~~~~ | ^~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: t/t_assoc_method_bad.v:19:13: The 2 arguments passed to .next method does not match its requiring 1 arguments %Error: t/t_assoc_method_bad.v:19:11: The 2 arguments passed to .next method does not match its requiring 1 arguments
: ... note: In instance 't' : ... note: In instance 't'
19 | v = a.next(k, "bad2"); 19 | v = a.next(k, "bad2");
| ^~~~ | ^~~~
%Error: t/t_assoc_method_bad.v:20:13: The 0 arguments passed to .last method does not match its requiring 1 arguments %Error: t/t_assoc_method_bad.v:20:11: The 0 arguments passed to .last method does not match its requiring 1 arguments
: ... note: In instance 't' : ... note: In instance 't'
20 | v = a.last(); 20 | v = a.last();
| ^~~~ | ^~~~
%Error-UNSUPPORTED: t/t_assoc_method_bad.v:20:13: Unsupported: Non-variable on LHS of built-in method 'last' %Error-UNSUPPORTED: t/t_assoc_method_bad.v:20:11: Unsupported: Non-variable on LHS of built-in method 'last'
: ... note: In instance 't' : ... note: In instance 't'
20 | v = a.last(); 20 | v = a.last();
| ^~~~ | ^~~~
%Error: t/t_assoc_method_bad.v:21:13: The 2 arguments passed to .prev method does not match its requiring 1 arguments %Error: t/t_assoc_method_bad.v:21:11: The 2 arguments passed to .prev method does not match its requiring 1 arguments
: ... note: In instance 't' : ... note: In instance 't'
21 | v = a.prev(k, "bad2"); 21 | v = a.prev(k, "bad2");
| ^~~~ | ^~~~
%Error: t/t_assoc_method_bad.v:22:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments %Error: t/t_assoc_method_bad.v:22:7: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments
: ... note: In instance 't' : ... note: In instance 't'
22 | a.delete(k, "bad2"); 22 | a.delete(k, "bad2");
| ^~~~~~ | ^~~~~~
%Error: t/t_assoc_method_bad.v:24:9: Array method 'sort' not legal on associative arrays %Error: t/t_assoc_method_bad.v:24:7: Array method 'sort' not legal on associative arrays
: ... note: In instance 't' : ... note: In instance 't'
24 | a.sort; 24 | a.sort;
| ^~~~ | ^~~~
%Error: t/t_assoc_method_bad.v:25:9: Array method 'rsort' not legal on associative arrays %Error: t/t_assoc_method_bad.v:25:7: Array method 'rsort' not legal on associative arrays
: ... note: In instance 't' : ... note: In instance 't'
25 | a.rsort; 25 | a.rsort;
| ^~~~~ | ^~~~~
%Error: t/t_assoc_method_bad.v:26:9: Array method 'reverse' not legal on associative arrays %Error: t/t_assoc_method_bad.v:26:7: Array method 'reverse' not legal on associative arrays
: ... note: In instance 't' : ... note: In instance 't'
26 | a.reverse; 26 | a.reverse;
| ^~~~~~~ | ^~~~~~~
%Error: t/t_assoc_method_bad.v:27:9: Array method 'shuffle' not legal on associative arrays %Error: t/t_assoc_method_bad.v:27:7: Array method 'shuffle' not legal on associative arrays
: ... note: In instance 't' : ... note: In instance 't'
27 | a.shuffle; 27 | a.shuffle;
| ^~~~~~~ | ^~~~~~~
%Error: t/t_assoc_method_bad.v:29:9: Unknown built-in associative array method 'bad_not_defined' %Error: t/t_assoc_method_bad.v:29:7: Unknown built-in associative array method 'bad_not_defined'
: ... note: In instance 't' : ... note: In instance 't'
29 | a.bad_not_defined(); 29 | a.bad_not_defined();
| ^~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~

2
test_regress/t/t_assoc_method_bad.v
View File

@ -7,7 +7,7 @@
module t; module t;
initial begin initial begin
string a [string]; string a[string];
string k; string k;
string v; string v;

4
test_regress/t/t_assoc_method_map.out
View File

@ -1,6 +1,6 @@
%Error-UNSUPPORTED: t/t_assoc_method_map.v:17:15: Unsupported: Associative array 'map' method (IEEE 1800-2023 7.12.5) %Error-UNSUPPORTED: t/t_assoc_method_map.v:19:13: Unsupported: Associative array 'map' method (IEEE 1800-2023 7.12.5)
: ... note: In instance 't' : ... note: In instance 't'
17 | res = a.map(el) with (el == 2); 19 | res = a.map(el) with (el == 2);
| ^~~ | ^~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to %Error: Exiting due to

2
test_regress/t/t_assoc_method_map.v
View File

@ -4,8 +4,10 @@
// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-FileCopyrightText: 2024 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t; module t;

12
test_regress/t/t_assoc_ref_type.v
View File

@ -31,7 +31,9 @@ class Bar;
endfunction endfunction
endclass endclass
class Baz #(type T=Foo1); class Baz #(
type T = Foo1
);
protected T m_dict[int]; protected T m_dict[int];
function void set(int key); function void set(int key);
@ -46,7 +48,9 @@ endclass
class WBase; class WBase;
endclass endclass
class Wrapper#(type VAL_T=int); class Wrapper #(
type VAL_T = int
);
VAL_T value; VAL_T value;
endclass endclass
@ -71,8 +75,8 @@ module t;
automatic Baz #(Foo2) baz_2_i = new; automatic Baz #(Foo2) baz_2_i = new;
automatic Bum bum_i; automatic Bum bum_i;
automatic Wrapper#(wrap_map_t) wrap_map = new(); automatic Wrapper #(wrap_map_t) wrap_map = new();
automatic Wrapper#(wrap_queue_t) wrap_queue = new(); automatic Wrapper #(wrap_queue_t) wrap_queue = new();
bar_i.set(1); bar_i.set(1);
baz_1_i.set(2); baz_1_i.set(2);

48
test_regress/t/t_assoc_wildcard.v
View File

@ -4,21 +4,21 @@
// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
integer cyc = 0; integer cyc = 0;
integer i; integer i;
always @ (posedge clk) begin always @(posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
begin begin
// Wildcard // Wildcard
@ -28,24 +28,36 @@ module t (/*AUTOARG*/
int k; int k;
string v; string v;
v = b["CCC"]; `checks(v, "baring"); v = b["CCC"];
v = b["BBBBB"]; `checks(v, "fooing"); `checks(v, "baring");
v = b["BBBBB"];
`checks(v, "fooing");
v = a["CCC"]; `checks(v, "baring"); v = a["CCC"];
v = a["BBBBB"]; `checks(v, "fooing"); `checks(v, "baring");
v = a["BBBBB"];
`checks(v, "fooing");
a[32'd1234] = "fooed"; a[32'd1234] = "fooed";
a[4'd3] = "bared"; a[4'd3] = "bared";
a[79'h4141] = "bazed"; a[79'h4141] = "bazed";
i = a.num(); `checkh(i, 5); i = a.num();
i = a.size(); `checkh(i, 5); `checkh(i, 5);
v = a[39'd1234]; `checks(v, "fooed"); i = a.size();
v = a["AA"]; `checks(v, "bazed"); `checkh(i, 5);
v = a[4'd3]; `checks(v, "bared"); v = a[39'd1234];
i = a.exists("baz"); `checkh(i, 0); `checks(v, "fooed");
i = a.exists(4'd3); `checkh(i, 1); v = a["AA"];
`checks(v, "bazed");
v = a[4'd3];
`checks(v, "bared");
i = a.exists("baz");
`checkh(i, 0);
i = a.exists(4'd3);
`checkh(i, 1);
a.delete(4'd3); a.delete(4'd3);
i = a.size(); `checkh(i, 4); i = a.size();
`checkh(i, 4);
end end
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");

38
test_regress/t/t_assoc_wildcard_bad.out
View File

@ -1,77 +1,77 @@
%Error: t/t_assoc_wildcard_bad.v:23:13: The 1 arguments passed to .num method does not match its requiring 0 arguments %Error: t/t_assoc_wildcard_bad.v:23:11: The 1 arguments passed to .num method does not match its requiring 0 arguments
: ... note: In instance 't' : ... note: In instance 't'
23 | v = a.num("badarg"); 23 | v = a.num("badarg");
| ^~~ | ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_assoc_wildcard_bad.v:24:13: The 1 arguments passed to .size method does not match its requiring 0 arguments %Error: t/t_assoc_wildcard_bad.v:24:11: The 1 arguments passed to .size method does not match its requiring 0 arguments
: ... note: In instance 't' : ... note: In instance 't'
24 | v = a.size("badarg"); 24 | v = a.size("badarg");
| ^~~~ | ^~~~
%Error: t/t_assoc_wildcard_bad.v:25:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments %Error: t/t_assoc_wildcard_bad.v:25:11: The 0 arguments passed to .exists method does not match its requiring 1 arguments
: ... note: In instance 't' : ... note: In instance 't'
25 | v = a.exists(); 25 | v = a.exists();
| ^~~~~~ | ^~~~~~
%Error: t/t_assoc_wildcard_bad.v:26:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments %Error: t/t_assoc_wildcard_bad.v:26:11: The 2 arguments passed to .exists method does not match its requiring 1 arguments
: ... note: In instance 't' : ... note: In instance 't'
26 | v = a.exists(k, "bad2"); 26 | v = a.exists(k, "bad2");
| ^~~~~~ | ^~~~~~
%Error: t/t_assoc_wildcard_bad.v:27:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments %Error: t/t_assoc_wildcard_bad.v:27:7: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments
: ... note: In instance 't' : ... note: In instance 't'
27 | a.delete(k, "bad2"); 27 | a.delete(k, "bad2");
| ^~~~~~ | ^~~~~~
%Error: t/t_assoc_wildcard_bad.v:29:9: Array method 'sort' not legal on associative arrays %Error: t/t_assoc_wildcard_bad.v:29:7: Array method 'sort' not legal on associative arrays
: ... note: In instance 't' : ... note: In instance 't'
29 | a.sort; 29 | a.sort;
| ^~~~ | ^~~~
%Error: t/t_assoc_wildcard_bad.v:30:9: Array method 'rsort' not legal on associative arrays %Error: t/t_assoc_wildcard_bad.v:30:7: Array method 'rsort' not legal on associative arrays
: ... note: In instance 't' : ... note: In instance 't'
30 | a.rsort; 30 | a.rsort;
| ^~~~~ | ^~~~~
%Error: t/t_assoc_wildcard_bad.v:31:9: Array method 'reverse' not legal on associative arrays %Error: t/t_assoc_wildcard_bad.v:31:7: Array method 'reverse' not legal on associative arrays
: ... note: In instance 't' : ... note: In instance 't'
31 | a.reverse; 31 | a.reverse;
| ^~~~~~~ | ^~~~~~~
%Error: t/t_assoc_wildcard_bad.v:32:9: Array method 'shuffle' not legal on associative arrays %Error: t/t_assoc_wildcard_bad.v:32:7: Array method 'shuffle' not legal on associative arrays
: ... note: In instance 't' : ... note: In instance 't'
32 | a.shuffle; 32 | a.shuffle;
| ^~~~~~~ | ^~~~~~~
%Error: t/t_assoc_wildcard_bad.v:34:9: Array method 'first' not legal on wildcard associative arrays %Error: t/t_assoc_wildcard_bad.v:34:7: Array method 'first' not legal on wildcard associative arrays
: ... note: In instance 't' : ... note: In instance 't'
34 | a.first; 34 | a.first;
| ^~~~~ | ^~~~~
%Error: t/t_assoc_wildcard_bad.v:35:9: Array method 'last' not legal on wildcard associative arrays %Error: t/t_assoc_wildcard_bad.v:35:7: Array method 'last' not legal on wildcard associative arrays
: ... note: In instance 't' : ... note: In instance 't'
35 | a.last; 35 | a.last;
| ^~~~ | ^~~~
%Error: t/t_assoc_wildcard_bad.v:36:9: Array method 'next' not legal on wildcard associative arrays %Error: t/t_assoc_wildcard_bad.v:36:7: Array method 'next' not legal on wildcard associative arrays
: ... note: In instance 't' : ... note: In instance 't'
36 | a.next; 36 | a.next;
| ^~~~ | ^~~~
%Error: t/t_assoc_wildcard_bad.v:37:9: Array method 'prev' not legal on wildcard associative arrays %Error: t/t_assoc_wildcard_bad.v:37:7: Array method 'prev' not legal on wildcard associative arrays
: ... note: In instance 't' : ... note: In instance 't'
37 | a.prev; 37 | a.prev;
| ^~~~ | ^~~~
%Error: t/t_assoc_wildcard_bad.v:38:9: Array method 'unique_index' not legal on wildcard associative arrays %Error: t/t_assoc_wildcard_bad.v:38:7: Array method 'unique_index' not legal on wildcard associative arrays
: ... note: In instance 't' : ... note: In instance 't'
38 | a.unique_index; 38 | a.unique_index;
| ^~~~~~~~~~~~ | ^~~~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:39:9: Array method 'find_index' not legal on wildcard associative arrays %Error: t/t_assoc_wildcard_bad.v:39:7: Array method 'find_index' not legal on wildcard associative arrays
: ... note: In instance 't' : ... note: In instance 't'
39 | a.find_index; 39 | a.find_index;
| ^~~~~~~~~~ | ^~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:40:9: Array method 'find_first_index' not legal on wildcard associative arrays %Error: t/t_assoc_wildcard_bad.v:40:7: Array method 'find_first_index' not legal on wildcard associative arrays
: ... note: In instance 't' : ... note: In instance 't'
40 | a.find_first_index; 40 | a.find_first_index;
| ^~~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:41:9: Array method 'find_last_index' not legal on wildcard associative arrays %Error: t/t_assoc_wildcard_bad.v:41:7: Array method 'find_last_index' not legal on wildcard associative arrays
: ... note: In instance 't' : ... note: In instance 't'
41 | a.find_last_index; 41 | a.find_last_index;
| ^~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~
%Error: t/t_assoc_wildcard_bad.v:43:8: Wildcard index must be integral (IEEE 1800-2023 7.8.1) %Error: t/t_assoc_wildcard_bad.v:43:6: Wildcard index must be integral (IEEE 1800-2023 7.8.1)
: ... note: In instance 't' : ... note: In instance 't'
43 | a[x] = "bad"; 43 | a[x] = "bad";
| ^ | ^
%Error: t/t_assoc_wildcard_bad.v:45:9: Unknown wildcard associative array method 'bad_not_defined' %Error: t/t_assoc_wildcard_bad.v:45:7: Unknown wildcard associative array method 'bad_not_defined'
: ... note: In instance 't' : ... note: In instance 't'
45 | a.bad_not_defined(); 45 | a.bad_not_defined();
| ^~~~~~~~~~~~~~~ | ^~~~~~~~~~~~~~~

2
test_regress/t/t_assoc_wildcard_map.out
View File

@ -1,4 +1,4 @@
%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5) %Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:13: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5)
: ... note: In instance 't' : ... note: In instance 't'
19 | res = a.map(el) with (el == 2); 19 | res = a.map(el) with (el == 2);
| ^~~ | ^~~

2
test_regress/t/t_assoc_wildcard_method.v
View File

@ -4,9 +4,11 @@
// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-FileCopyrightText: 2019 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
// verilog_format: on
module t; module t;
typedef struct { int x, y; } point; typedef struct { int x, y; } point;

11
test_regress/t/t_attr_parenstar.v
View File

@ -4,13 +4,11 @@
// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-FileCopyrightText: 2011 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
// verilog_format: off
always @(*) begin always @(*) begin
if (clk) begin end if (clk) begin end
end end
@ -34,6 +32,7 @@ module t (/*AUTOARG*/
) begin ) begin
if (clk) begin end if (clk) begin end
end end
// verilog_format: on
initial begin initial begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");

80
test_regress/t/t_benchmark_mux4k.v
View File

@ -18,10 +18,10 @@
// Total of DATA_WIDTH*MUX2_SIZE*(MUX1_SIZE+1) instantiations of mux64 // Total of DATA_WIDTH*MUX2_SIZE*(MUX1_SIZE+1) instantiations of mux64
module t (/*AUTOARG*/ module t ( /*AUTOARG*/
// Inputs // Inputs
clk clk
); );
input clk; input clk;
/*AUTOWIRE*/ /*AUTOWIRE*/
@ -33,12 +33,13 @@ module t (/*AUTOARG*/
reg [`ADDR_WIDTH-1:0] addr; reg [`ADDR_WIDTH-1:0] addr;
// Mux: takes in addr and datai and outputs datao // Mux: takes in addr and datai and outputs datao
mux4096 mux4096 (/*AUTOINST*/ mux4096 mux4096 ( /*AUTOINST*/
// Outputs // Outputs
.datao (datao[`DATA_WIDTH-1:0]), .datao(datao[`DATA_WIDTH-1:0]),
// Inputs // Inputs
.datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]), .datai(datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]),
.addr (addr[`ADDR_WIDTH-1:0])); .addr(addr[`ADDR_WIDTH-1:0])
);
// calculate what the answer should be from datai. This is bit // calculate what the answer should be from datai. This is bit
@ -47,21 +48,21 @@ module t (/*AUTOARG*/
reg [`DATA_WIDTH-1:0] datao_check; reg [`DATA_WIDTH-1:0] datao_check;
integer j; integer j;
always @(datai or addr) begin always @(datai or addr) begin
for(j=0;j<`DATA_WIDTH;j=j+1) begin for (j = 0; j < `DATA_WIDTH; j = j + 1) begin
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr); datao_check[j] = datai >> ((`MUX1_SIZE * `MUX2_SIZE * j) + addr);
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
end end
end end
// Run the test loop. This just increments the address // Run the test loop. This just increments the address
integer i, result; integer i, result;
always @ (posedge clk) begin always @(posedge clk) begin
// initial the input data with random values // initial the input data with random values
if (addr == 0) begin if (addr == 0) begin
result = 1; result = 1;
datai = 0; datai = 0;
for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin for (i = 0; i < `MUX1_SIZE * `MUX2_SIZE; i = i + 1) begin
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}}); datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}});
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
@ -86,25 +87,25 @@ module t (/*AUTOARG*/
endmodule endmodule
module mux4096 module mux4096 (
(input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai, input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai,
input [`ADDR_WIDTH-1:0] addr, input [`ADDR_WIDTH-1:0] addr,
output [`DATA_WIDTH-1:0] datao output [`DATA_WIDTH-1:0] datao
); );
// DATA_WIDTH instantiations of mux4096_1bit // DATA_WIDTH instantiations of mux4096_1bit
mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0] mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0] (
(.addr(addr), .addr(addr),
.datai(datai), .datai(datai),
.datao(datao) .datao(datao)
); );
endmodule endmodule
module mux4096_1bit module mux4096_1bit (
(input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai, input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai,
input [`ADDR_WIDTH-1:0] addr, input [`ADDR_WIDTH-1:0] addr,
output datao output datao
); );
// address decoding // address decoding
wire [3:0] A = (4'b1) << addr[1:0]; wire [3:0] A = (4'b1) << addr[1:0];
@ -118,36 +119,43 @@ module mux4096_1bit
// DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64 // DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64
// first stage of 64:1 muxing // first stage of 64:1 muxing
mux64 #(.MUX_SIZE(`MUX1_SIZE)) mux1[`MUX2_SIZE-1:0] mux64 #(
(.A(A), .MUX_SIZE(`MUX1_SIZE)
) mux1[`MUX2_SIZE-1:0] (
.A(A),
.B(B), .B(B),
.C(C), .C(C),
.datai(datai), .datai(datai),
.datao(data0)); .datao(data0)
);
// DATA_WIDTH*MUX2_SIZE instantiations of mux64 // DATA_WIDTH*MUX2_SIZE instantiations of mux64
// second stage of 64:1 muxing // second stage of 64:1 muxing
mux64 #(.MUX_SIZE(`MUX2_SIZE)) mux2 mux64 #(
(.A(D), .MUX_SIZE(`MUX2_SIZE)
) mux2 (
.A(D),
.B(E), .B(E),
.C(F), .C(F),
.datai(data0), .datai(data0),
.datao(datao)); .datao(datao)
);
endmodule endmodule
module mux64 module mux64 #(
#(parameter MUX_SIZE=64) parameter MUX_SIZE = 64
(input [3:0] A, ) (
input [3:0] A,
input [3:0] B, input [3:0] B,
input [3:0] C, input [3:0] C,
input [MUX_SIZE-1:0] datai, input [MUX_SIZE-1:0] datai,
output datao output datao
); );
wire [63:0] colSelA = { 16{ A[3:0] }}; wire [63:0] colSelA = {16{A[3:0]}};
wire [63:0] colSelB = { 4{ {4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}}; wire [63:0] colSelB = {4{{4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}};
wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}}; wire [63:0] colSelC = {{16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}};
wire [MUX_SIZE-1:0] data_bus; wire [MUX_SIZE-1:0] data_bus;
@ -156,8 +164,8 @@ module mux64
//.colSelB(colSelB[MUX_SIZE-1:0]), //.colSelB(colSelB[MUX_SIZE-1:0]),
//.colSelC(colSelC[MUX_SIZE-1:0]), //.colSelC(colSelC[MUX_SIZE-1:0]),
drv drv[MUX_SIZE-1:0] drv drv[MUX_SIZE-1:0] (
(.colSelA(colSelA[MUX_SIZE-1:0]), .colSelA(colSelA[MUX_SIZE-1:0]),
.colSelB(colSelB[MUX_SIZE-1:0]), .colSelB(colSelB[MUX_SIZE-1:0]),
.colSelC(colSelC[MUX_SIZE-1:0]), .colSelC(colSelC[MUX_SIZE-1:0]),
.datai(datai), .datai(datai),
@ -168,13 +176,13 @@ module mux64
endmodule endmodule
module drv module drv (
(input colSelA, input colSelA,
input colSelB, input colSelB,
input colSelC, input colSelC,
input datai, input datai,
output datao output datao
); );
assign datao = colSelC & colSelB & colSelA & datai; assign datao = colSelC & colSelB & colSelA & datai;
endmodule endmodule

47
test_regress/t/t_bind.v
View File

@ -7,7 +7,7 @@
bit a_finished; bit a_finished;
bit b_finished; bit b_finished;
module t (/*AUTOARG*/ module t ( /*AUTOARG*/
// Inputs // Inputs
clk clk
); );
@ -15,18 +15,17 @@ module t (/*AUTOARG*/
wire [31:0] o; wire [31:0] o;
wire si = 1'b0; wire si = 1'b0;
ExampInst i ExampInst i ( // Outputs
(// Outputs .o(o[31:0]),
.o (o[31:0]),
// Inputs // Inputs
.i (1'b0) .i(1'b0)
/*AUTOINST*/); /*AUTOINST*/);
Prog p (/*AUTOINST*/ Prog p ( /*AUTOINST*/
// Inputs // Inputs
.si (si)); .si (si));
always @ (posedge clk) begin always @(posedge clk) begin
if (!a_finished) $stop; if (!a_finished) $stop;
if (!b_finished) $stop; if (!b_finished) $stop;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
@ -38,41 +37,47 @@ endmodule
module InstModule ( module InstModule (
output logic [31:0] so, output logic [31:0] so,
input si input si
); );
assign so = {32{si}}; assign so = {32{si}};
endmodule endmodule
program Prog (input si); program Prog (
input si
);
initial a_finished = 1'b1; initial a_finished = 1'b1;
endprogram endprogram
module ExampInst (o,i); module ExampInst (
o,
i
);
output logic [31:0] o; output logic [31:0] o;
input i; input i;
InstModule instName InstModule instName ( // Outputs
(// Outputs .so(o[31:0]),
.so (o[31:0]),
// Inputs // Inputs
.si (i) .si(i)
/*AUTOINST*/); /*AUTOINST*/);
//bind InstModule Prog instProg //bind InstModule Prog instProg
// (.si(si)); // (.si(si));
// Note is based on context of caller // Note is based on context of caller
bind InstModule Prog instProg bind InstModule Prog instProg ( /*AUTOBIND*/
(/*AUTOBIND*/ .si(si)
.si (si)); );
endmodule endmodule
// Check bind at top level // Check bind at top level
bind InstModule Prog2 instProg2 bind InstModule Prog2 instProg2 ( /*AUTOBIND*/
(/*AUTOBIND*/ .si(si)
.si (si)); );
// Check program declared after bind // Check program declared after bind
program Prog2 (input si); program Prog2 (
input si
);
initial b_finished = 1'b1; initial b_finished = 1'b1;
endprogram endprogram

13
test_regress/t/t_bind2.v
View File

@ -6,14 +6,15 @@
// verilator lint_off WIDTH // verilator lint_off WIDTH
// verilog_format: off
`define stop $stop `define stop $stop
`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t (
input clk
);
module t ( /*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] p1; reg [7:0] p1;
reg [7:0] p2; reg [7:0] p2;
reg [7:0] p3; reg [7:0] p3;

6
test_regress/t/t_bind_nfound.v
View File

@ -9,7 +9,7 @@ endinterface
module t; module t;
sub sub(); sub sub ();
initial begin initial begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
@ -19,9 +19,9 @@ module t;
endmodule endmodule
module sub_ext; module sub_ext;
bind sub_inst bound_if i_bound(); bind sub_inst bound_if i_bound ();
endmodule endmodule
module sub; module sub;
sub_ext sub_ext(); sub_ext sub_ext ();
endmodule endmodule

14
test_regress/t/t_bitsel_2d_slice.v
View File

@ -4,15 +4,13 @@
// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-FileCopyrightText: 2025 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
localparam int WIDTH = 8; localparam int WIDTH = 8;
typedef logic [WIDTH-1:0] [15:0] two_dee_t; typedef logic [WIDTH-1:0][15:0] two_dee_t;
typedef logic[$clog2(WIDTH)-1:0] index_t; typedef logic [$clog2(WIDTH)-1:0] index_t;
two_dee_t the_two_dee; two_dee_t the_two_dee;
@ -21,7 +19,7 @@ module t (/*AUTOARG*/
the_two_dee[index_t'(5)][15:8] = 8'h12; the_two_dee[index_t'(5)][15:8] = 8'h12;
end end
always @ (posedge clk) begin always @(posedge clk) begin
if (the_two_dee[5] != 16'h12ab) $stop(); if (the_two_dee[5] != 16'h12ab) $stop();
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;

2
test_regress/t/t_bitsel_const_bad.out
View File

@ -1,4 +1,4 @@
%Error: t/t_bitsel_const_bad.v:16:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' %Error: t/t_bitsel_const_bad.v:16:15: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic'
: ... note: In instance 't' : ... note: In instance 't'
16 | assign a = b[0]; 16 | assign a = b[0];
| ^ | ^

9
test_regress/t/t_bitsel_enum.v
View File

@ -4,17 +4,14 @@
// SPDX-FileCopyrightText: 2015 Jonathon Donaldson // SPDX-FileCopyrightText: 2015 Jonathon Donaldson
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t_bitsel_enum module t_bitsel_enum (
(
output out0, output out0,
output out1 output out1
); );
localparam [6:0] CNST_VAL = 7'h22; localparam [6:0] CNST_VAL = 7'h22;
enum logic [6:0] { enum logic [6:0] {ENUM_VAL = 7'h33} MyEnum;
ENUM_VAL = 7'h33
} MyEnum;
assign out0 = CNST_VAL[0]; assign out0 = CNST_VAL[0];
// Not supported by NC-verilog nor VCS, but other simulators do // Not supported by NC-verilog nor VCS, but other simulators do

9
test_regress/t/t_bitsel_over32.v
View File

@ -4,7 +4,10 @@
// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-FileCopyrightText: 2025 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t(aw_addr, orig_aw_size); module t (
aw_addr,
orig_aw_size
);
typedef logic [63:0] addr_t; typedef logic [63:0] addr_t;
typedef logic [7:0][7:0] mst_data_t; typedef logic [7:0][7:0] mst_data_t;
@ -22,7 +25,7 @@ module t(aw_addr, orig_aw_size);
w_data = '0; w_data = '0;
for (int b=0; b<16; b++) begin for (int b = 0; b < 16; b++) begin
if ((b >= slv_port_offset) && if ((b >= slv_port_offset) &&
(b - slv_port_offset < (1 << orig_aw_size)) && (b - slv_port_offset < (1 << orig_aw_size)) &&
(b + mst_port_offset - slv_port_offset < 8)) begin (b + mst_port_offset - slv_port_offset < 8)) begin
@ -30,7 +33,7 @@ module t(aw_addr, orig_aw_size);
// verilator lint_on WIDTHEXPAND // verilator lint_on WIDTHEXPAND
// [#][7:0] = [ +: 8] // [#][7:0] = [ +: 8]
w_data[index] = slv_req_i_w_data[8*b +: 8]; w_data[index] = slv_req_i_w_data[8*b+:8];
end end
end end

30
test_regress/t/t_bitsel_slice.v
View File

@ -4,17 +4,15 @@
// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-FileCopyrightText: 2014 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/ module t (
// Inputs input clk
clk );
);
input clk;
integer cyc = 0; integer cyc = 0;
reg [63:0] crc; reg [63:0] crc;
reg [63:0] sum; reg [63:0] sum;
logic [2:0] [1:0] in; logic [2:0][1:0] in;
always @* in = crc[5:0]; always @* in = crc[5:0];
/*AUTOWIRE*/ /*AUTOWIRE*/
@ -22,7 +20,7 @@ module t (/*AUTOARG*/
logic [1:0] [1:0] out; // From test of Test.v logic [1:0] [1:0] out; // From test of Test.v
// End of automatics // End of automatics
Test test (/*AUTOINST*/ Test test ( /*AUTOINST*/
// Outputs // Outputs
.out (out/*[1:0][1:0]*/), .out (out/*[1:0][1:0]*/),
// Inputs // Inputs
@ -30,31 +28,31 @@ module t (/*AUTOARG*/
.in (in/*[2:0][1:0]*/)); .in (in/*[2:0][1:0]*/));
// Aggregate outputs into a single result vector // Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out[1],out[0]}; wire [63:0] result = {60'h0, out[1], out[0]};
// Test loop // Test loop
always @ (posedge clk) begin always @(posedge clk) begin
`ifdef TEST_VERBOSE `ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif `endif
cyc <= cyc + 1; cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin if (cyc == 0) begin
// Setup // Setup
crc <= 64'h5aef0c8d_d70a4497; crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0; sum <= 64'h0;
end end
else if (cyc<10) begin else if (cyc < 10) begin
sum <= 64'h0; sum <= 64'h0;
end end
else if (cyc<90) begin else if (cyc < 90) begin
end end
else if (cyc==99) begin else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop; if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match) // What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hdc21e42d85441511 `define EXPECTED_SUM 64'hdc21e42d85441511
if (sum !== `EXPECTED_SUM) $stop; if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
@ -63,7 +61,7 @@ module t (/*AUTOARG*/
endmodule endmodule
module Test (/*AUTOARG*/ module Test ( /*AUTOARG*/
// Outputs // Outputs
out, out,
// Inputs // Inputs
@ -78,6 +76,6 @@ module Test (/*AUTOARG*/
output logic [1:0][1:0] out; output logic [1:0][1:0] out;
always @(posedge clk) begin always @(posedge clk) begin
out <= in[2 -: 2]; out <= in[2-:2];
end end
endmodule endmodule

2
test_regress/t/t_bitsel_struct.v
View File

@ -20,7 +20,7 @@ module t;
reg [7:0] a; reg [7:0] a;
initial begin initial begin
b = {16'h8765,16'h4321,1'b1}; b = {16'h8765, 16'h4321, 1'b1};
a = b.channel[0][8+:8]; a = b.channel[0][8+:8];
if (a != 8'h43) $stop; if (a != 8'h43) $stop;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");

18
test_regress/t/t_bitsel_struct2.v
View File

@ -4,9 +4,11 @@
// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-FileCopyrightText: 2013 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop `define stop $stop
`define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t; module t;
@ -15,19 +17,17 @@ module t;
logic [5:4][3:2] b; logic [5:4][3:2] b;
} ab_t; } ab_t;
typedef ab_t [7:6] c_t; // array of structs typedef ab_t [7:6] c_t; // array of structs
typedef struct packed { typedef struct packed {c_t [17:16] d;} e_t;
c_t [17:16] d;
} e_t;
initial begin initial begin
e_t e; e_t e;
`checkh($bits(ab_t),6); `checkh($bits(ab_t), 6);
`checkh($bits(c_t),12); `checkh($bits(c_t), 12);
`checkh($bits(e_t),24); `checkh($bits(e_t), 24);
`checkh($bits(e), 24); `checkh($bits(e), 24);
`checkh($bits(e.d[17]),12); `checkh($bits(e.d[17]), 12);
`checkh($bits(e.d[16][6]),6); `checkh($bits(e.d[16][6]), 6);
`checkh($bits(e.d[16][6].b[5]),2); `checkh($bits(e.d[16][6].b[5]), 2);
`checkh($bits(e.d[16][6].b[5][2]), 1); `checkh($bits(e.d[16][6].b[5][2]), 1);
// //
e = 24'b101101010111010110101010; e = 24'b101101010111010110101010;

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