Support sequence throughout operator
This commit is contained in:
Yilou Wang
parent
04f410622b
commit
cd42b02a8f
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@ -474,6 +474,9 @@ private:
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AstEventControl* const controlp = new AstEventControl{
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nodep->fileline(), new AstSenTree{flp, sensesp->cloneTree(false)}, nullptr};
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const std::string delayName = m_cycleDlyNames.get(nodep);
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AstNodeExpr* throughoutp
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= nodep->throughoutp() ? nodep->throughoutp()->unlinkFrBack() : nullptr;
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AstVar* const cntVarp = new AstVar{flp, VVarType::BLOCKTEMP, delayName + "__counter",
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nodep->findBasicDType(VBasicDTypeKwd::UINT32)};
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cntVarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT);
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@ -481,24 +484,74 @@ private:
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AstBegin* const beginp = new AstBegin{flp, delayName + "__block", cntVarp, true};
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beginp->addStmtsp(new AstAssign{flp, new AstVarRef{flp, cntVarp, VAccess::WRITE}, valuep});
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// Throughout: create flag tracking whether condition held every tick
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AstVar* throughoutOkp = nullptr;
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if (throughoutp) {
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throughoutOkp
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= new AstVar{flp, VVarType::BLOCKTEMP, delayName + "__throughoutOk",
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nodep->findBasicDType(VBasicDTypeKwd::LOGIC_IMPLICIT)};
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throughoutOkp->lifetime(VLifetime::AUTOMATIC_EXPLICIT);
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beginp->addStmtsp(throughoutOkp);
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beginp->addStmtsp(
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new AstAssign{flp, new AstVarRef{flp, throughoutOkp, VAccess::WRITE},
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new AstConst{flp, AstConst::BitTrue{}}});
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// Check condition at tick 0 (sequence start, before entering loop)
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AstSampled* const initSampledp
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= new AstSampled{flp, throughoutp->cloneTreePure(false)};
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initSampledp->dtypeSetBit();
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beginp->addStmtsp(
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new AstIf{flp, new AstLogNot{flp, initSampledp},
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new AstAssign{flp, new AstVarRef{flp, throughoutOkp, VAccess::WRITE},
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new AstConst{flp, AstConst::BitFalse{}}}});
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}
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{
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AstLoop* const loopp = new AstLoop{flp};
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loopp->addStmtsp(new AstLoopTest{
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flp, loopp,
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new AstGt{flp, new AstVarRef{flp, cntVarp, VAccess::READ}, new AstConst{flp, 0}}});
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// When throughout is present, exit loop early if condition fails
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AstNodeExpr* loopCondp
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= new AstGt{flp, new AstVarRef{flp, cntVarp, VAccess::READ}, new AstConst{flp, 0}};
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if (throughoutOkp) {
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loopCondp = new AstLogAnd{flp, loopCondp,
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new AstVarRef{flp, throughoutOkp, VAccess::READ}};
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}
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loopp->addStmtsp(new AstLoopTest{flp, loopp, loopCondp});
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loopp->addStmtsp(controlp);
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loopp->addStmtsp(
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new AstAssign{flp, new AstVarRef{flp, cntVarp, VAccess::WRITE},
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new AstSub{flp, new AstVarRef{flp, cntVarp, VAccess::READ},
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new AstConst{flp, 1}}});
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// Check throughout condition at each tick during delay (IEEE 1800-2023 16.9.9)
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if (throughoutp) {
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AstSampled* const sampledp = new AstSampled{flp, throughoutp};
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sampledp->dtypeSetBit();
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loopp->addStmtsp(
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new AstIf{flp, new AstLogNot{flp, sampledp},
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new AstAssign{flp,
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new AstVarRef{flp, throughoutOkp, VAccess::WRITE},
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new AstConst{flp, AstConst::BitFalse{}}}});
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}
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beginp->addStmtsp(loopp);
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}
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if (m_disableSeqIfp) {
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// Compose wrappers on remaining sequence: throughout gate (inner), disable iff (outer)
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AstNode* remainp = nodep->nextp() ? nodep->nextp()->unlinkFrBackWithNext() : nullptr;
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if (throughoutOkp) {
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// If condition failed during delay, fail assertion
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remainp = new AstIf{flp, new AstVarRef{flp, throughoutOkp, VAccess::READ}, remainp,
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new AstPExprClause{flp, /*pass=*/false}};
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}
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if (m_disableSeqIfp && remainp) {
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AstIf* const disableSeqIfp = m_disableSeqIfp->cloneTree(false);
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AstNode* const continuationsp = nodep->nextp()->unlinkFrBackWithNext();
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// Keep continuation statements in a proper statement-list container.
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disableSeqIfp->addThensp(new AstBegin{flp, "", continuationsp, true});
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nodep->addNextHere(disableSeqIfp);
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disableSeqIfp->addThensp(new AstBegin{flp, "", remainp, true});
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remainp = disableSeqIfp;
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}
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if (remainp) {
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if (throughoutOkp) {
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// throughoutOkp is declared in beginp scope -- check must be inside it
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beginp->addStmtsp(remainp);
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} else {
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nodep->addNextHere(remainp);
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}
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}
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nodep->replaceWith(beginp);
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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@ -422,6 +422,45 @@ class AssertPropLowerVisitor final : public VNVisitor {
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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}
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}
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void visit(AstSExprThroughout* nodep) override {
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// IEEE 1800-2023 16.9.9: expr throughout seq
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// Transform by AND-ing cond with every leaf expression in the sequence,
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// and attaching cond to every delay for per-tick checking in V3AssertPre.
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AstNodeExpr* const condp = nodep->condp()->unlinkFrBack();
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AstNodeExpr* const seqp = nodep->seqp()->unlinkFrBack();
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if (AstSExpr* const sexprp = VN_CAST(seqp, SExpr)) {
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// Walk all SExpr nodes: AND cond with leaf expressions, attach to delays
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sexprp->foreach([&](AstSExpr* sp) {
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if (sp->exprp() && !VN_IS(sp->exprp(), SExpr)) {
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AstNodeExpr* const origp = sp->exprp()->unlinkFrBack();
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AstLogAnd* const andp
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= new AstLogAnd{origp->fileline(), condp->cloneTreePure(false), origp};
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andp->dtypeSetBit();
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sp->exprp(andp);
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}
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if (sp->preExprp() && !VN_IS(sp->preExprp(), SExpr)) {
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AstNodeExpr* const origp = sp->preExprp()->unlinkFrBack();
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AstLogAnd* const andp
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= new AstLogAnd{origp->fileline(), condp->cloneTreePure(false), origp};
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andp->dtypeSetBit();
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sp->preExprp(andp);
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}
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if (AstDelay* const dlyp = VN_CAST(sp->delayp(), Delay)) {
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dlyp->throughoutp(condp->cloneTreePure(false));
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}
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});
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nodep->replaceWith(sexprp);
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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VL_DO_DANGLING(condp->deleteTree(), condp);
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visit(sexprp);
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} else {
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// Single expression (no delay): degenerate to cond && seq
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AstLogAnd* const andp = new AstLogAnd{nodep->fileline(), condp, seqp};
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andp->dtypeSetBit();
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nodep->replaceWith(andp);
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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}
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}
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void visit(AstNodeModule* nodep) override {
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VL_RESTORER(m_modp);
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m_modp = nodep;
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@ -982,6 +1021,40 @@ class RangeDelayExpander final : public VNVisitor {
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}
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}
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void visit(AstSExprThroughout* nodep) override {
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// Reject throughout with range-delay sequences before FSM expansion
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// would silently lose per-tick enforcement (IEEE 1800-2023 16.9.9)
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if (AstSExpr* const sexprp = VN_CAST(nodep->seqp(), SExpr)) {
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if (containsRangeDelay(sexprp)) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: throughout with range delay sequence");
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nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}});
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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return;
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}
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}
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// Reject throughout with nested throughout or goto repetition
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if (VN_IS(nodep->seqp(), SExprThroughout) || VN_IS(nodep->seqp(), SExprGotoRep)) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: throughout with complex sequence operator");
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nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}});
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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return;
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}
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// Reject throughout with temporal SAnd/SOr (containing SExpr = multi-cycle).
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// Pure boolean SAnd/SOr are OK -- AssertPropLowerVisitor lowers them to LogAnd/LogOr.
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if (VN_IS(nodep->seqp(), SAnd) || VN_IS(nodep->seqp(), SOr)) {
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bool hasSExpr = false;
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nodep->seqp()->foreach([&](const AstSExpr*) { hasSExpr = true; });
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if (hasSExpr) {
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nodep->v3warn(E_UNSUPPORTED,
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"Unsupported: throughout with complex sequence operator");
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nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}});
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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return;
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}
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}
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iterateChildren(nodep);
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}
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void visit(AstNode* nodep) override { iterateChildren(nodep); }
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public:
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@ -2181,6 +2181,21 @@ public:
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string emitC() override { V3ERROR_NA_RETURN(""); }
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bool cleanOut() const override { V3ERROR_NA_RETURN(""); }
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};
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class AstSExprThroughout final : public AstNodeExpr {
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// expr throughout seq (IEEE 1800-2023 16.9.9)
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// @astgen op1 := condp : AstNodeExpr // Boolean LHS
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// @astgen op2 := seqp : AstNodeExpr // Sequence RHS
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public:
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AstSExprThroughout(FileLine* fl, AstNodeExpr* condp, AstNodeExpr* seqp)
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: ASTGEN_SUPER_SExprThroughout(fl) {
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this->condp(condp);
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this->seqp(seqp);
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}
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ASTGEN_MEMBERS_AstSExprThroughout;
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string emitVerilog() override { V3ERROR_NA_RETURN(""); }
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string emitC() override { V3ERROR_NA_RETURN(""); }
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bool cleanOut() const override { V3ERROR_NA_RETURN(""); }
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};
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class AstSFormatArg final : public AstNodeExpr {
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// Information for formatting each argument to AstSFormat,
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// used to pass to (potentially) runtime decoding of format arguments
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@ -544,6 +544,7 @@ class AstDelay final : public AstNodeStmt {
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// @astgen op1 := lhsp : AstNodeExpr // Delay value (or min for range)
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// @astgen op2 := stmtsp : List[AstNode] // Statements under delay
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// @astgen op3 := rhsp : Optional[AstNodeExpr] // Max delay value (range delay only)
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// @astgen op4 := throughoutp : Optional[AstNodeExpr] // Throughout condition (IEEE 16.9.9)
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VTimescale m_timeunit; // Delay's time unit
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const bool m_isCycle; // True if it is a cycle delay
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@ -1067,6 +1067,11 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst {
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}
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iterateConst(nodep->exprp());
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}
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void visit(AstSExprThroughout* nodep) override {
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iterateConst(nodep->condp());
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puts(" throughout ");
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iterateConst(nodep->seqp());
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}
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// Terminals
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void visit(AstVarRef* nodep) override {
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@ -1645,6 +1645,24 @@ class WidthVisitor final : public VNVisitor {
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nodep->dtypeSetBit();
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}
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}
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void visit(AstSExprThroughout* nodep) override {
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m_hasSExpr = true;
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assertAtExpr(nodep);
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if (m_vup->prelim()) {
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// condp is a boolean expression, not a sequence -- clear m_underSExpr
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{
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VL_RESTORER(m_underSExpr);
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m_underSExpr = false;
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iterateCheckBool(nodep, "condp", nodep->condp(), BOTH);
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}
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{
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VL_RESTORER(m_underSExpr);
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m_underSExpr = true;
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iterate(nodep->seqp());
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}
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nodep->dtypeSetBit();
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}
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}
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void visit(AstSExpr* nodep) override {
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VL_RESTORER(m_underSExpr);
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m_underSExpr = true;
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@ -6849,7 +6849,7 @@ sexpr<nodeExprp>: // ==IEEE: sequence_expr (The name sexpr is important as reg
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| yFIRST_MATCH '(' sexpr ',' sequence_match_itemList ')'
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{ $$ = $3; BBUNSUP($1, "Unsupported: first_match (in sequence expression)"); DEL($5); }
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| ~p~sexpr/*sexpression_or_dist*/ yTHROUGHOUT sexpr
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{ $$ = $1; BBUNSUP($2, "Unsupported: throughout (in sequence expression)"); DEL($3); }
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{ $$ = new AstSExprThroughout{$2, $1, $3}; }
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// // Below pexpr's are really sequence_expr, but avoid conflict
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// // IEEE: sexpr yWITHIN sexpr
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| ~p~sexpr yWITHIN sexpr
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing'])
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test.execute()
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test.passes()
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@ -0,0 +1,67 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// IEEE 1800-2023 16.9.9: expr throughout seq
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// CRC-driven random stimulus exercises throughout with varying cond/a/b signals.
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc = '0;
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// Derive signals from non-adjacent CRC bits (gap > max delay to avoid LFSR correlation)
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wire cond = crc[0];
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wire a = crc[4];
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wire b = crc[8];
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int count_fail1 = 0;
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int count_fail2 = 0;
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int count_fail3 = 0;
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// Test 1: a |-> (cond throughout (1'b1 ##3 1'b1))
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// If a fires, cond must hold for 4 consecutive ticks (start + 3 delay ticks).
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assert property (@(posedge clk) disable iff (cyc < 10)
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a |-> (cond throughout (1'b1 ##3 1'b1)))
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else count_fail1 <= count_fail1 + 1;
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// Test 2: a |-> (cond throughout (1'b1 ##1 b))
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// If a fires, cond must hold for 2 ticks and b must be true at tick +1.
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assert property (@(posedge clk) disable iff (cyc < 10)
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a |-> (cond throughout (1'b1 ##1 b)))
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else count_fail2 <= count_fail2 + 1;
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// Test 3: a |-> (cond throughout b)
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// No delay: degenerates to a |-> (cond && b).
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assert property (@(posedge clk) disable iff (cyc < 10)
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a |-> (cond throughout b))
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else count_fail3 <= count_fail3 + 1;
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always_ff @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x cond=%b a=%b b=%b\n",
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$time, cyc, crc, cond, a, b);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 0) begin
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crc <= 64'h5aef0c8d_d70a4497;
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end else if (cyc == 99) begin
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`checkh(crc, 64'hc77bb9b3784ea091);
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`checkd(count_fail1, 36);
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`checkd(count_fail2, 37);
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`checkd(count_fail3, 31);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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@ -0,0 +1,10 @@
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%Error-UNSUPPORTED: t/t_sequence_sexpr_throughout_unsup.v:14:16: Unsupported: throughout with range delay sequence
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: ... note: In instance 't'
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14 | a |-> (a throughout (b ##[1:2] c)));
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| ^~~~~~~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_sequence_sexpr_throughout_unsup.v:18:16: Unsupported: throughout with complex sequence operator
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: ... note: In instance 't'
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18 | a |-> (a throughout ((b ##1 c) and (c ##1 b))));
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| ^~~~~~~~~~
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%Error: Exiting due to
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.lint(expect_filename=test.golden_filename,
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verilator_flags2=['--assert --timing --error-limit 1000'],
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fails=True)
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test.passes()
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@ -0,0 +1,20 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (
|
||||
input clk
|
||||
);
|
||||
logic a, b, c;
|
||||
|
||||
// Unsupported: throughout with range delay on RHS (IEEE 16.9.9)
|
||||
assert property (@(posedge clk)
|
||||
a |-> (a throughout (b ##[1:2] c)));
|
||||
|
||||
// Unsupported: throughout with temporal 'and' sequence on RHS
|
||||
assert property (@(posedge clk)
|
||||
a |-> (a throughout ((b ##1 c) and (c ##1 b))));
|
||||
|
||||
endmodule
|
||||
|
|
@ -2,72 +2,69 @@
|
|||
34 | a within(b);
|
||||
| ^~~~~~
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:46:7: Unsupported: throughout (in sequence expression)
|
||||
46 | a throughout b;
|
||||
| ^~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:50:7: Unsupported: intersect (in sequence expression)
|
||||
50 | a intersect b;
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:46:7: Unsupported: intersect (in sequence expression)
|
||||
46 | a intersect b;
|
||||
| ^~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:63:5: Unsupported: ## [*] cycle delay range expression
|
||||
63 | ## [*] b;
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:59:5: Unsupported: ## [*] cycle delay range expression
|
||||
59 | ## [*] b;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:66:5: Unsupported: ## [+] cycle delay range expression
|
||||
66 | ## [+] b;
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:62:5: Unsupported: ## [+] cycle delay range expression
|
||||
62 | ## [+] b;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:79:7: Unsupported: ## [*] cycle delay range expression
|
||||
79 | a ## [*] b;
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:75:7: Unsupported: ## [*] cycle delay range expression
|
||||
75 | a ## [*] b;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:82:7: Unsupported: ## [+] cycle delay range expression
|
||||
82 | a ## [+] b;
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:78:7: Unsupported: ## [+] cycle delay range expression
|
||||
78 | a ## [+] b;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:89:7: Unsupported: [*] boolean abbrev expression
|
||||
89 | a [*];
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:85:7: Unsupported: [*] boolean abbrev expression
|
||||
85 | a [*];
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:89:7: Unsupported: boolean abbrev (in sequence expression)
|
||||
89 | a [*];
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:85:7: Unsupported: boolean abbrev (in sequence expression)
|
||||
85 | a [*];
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:92:7: Unsupported: [+] boolean abbrev expression
|
||||
92 | a [+];
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:88:7: Unsupported: [+] boolean abbrev expression
|
||||
88 | a [+];
|
||||
| ^~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:92:7: Unsupported: boolean abbrev (in sequence expression)
|
||||
92 | a [+];
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:88:7: Unsupported: boolean abbrev (in sequence expression)
|
||||
88 | a [+];
|
||||
| ^~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:95:7: Unsupported: [= boolean abbrev expression
|
||||
95 | a [= 1];
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:7: Unsupported: [= boolean abbrev expression
|
||||
91 | a [= 1];
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:95:10: Unsupported: boolean abbrev (in sequence expression)
|
||||
95 | a [= 1];
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:10: Unsupported: boolean abbrev (in sequence expression)
|
||||
91 | a [= 1];
|
||||
| ^
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:98:7: Unsupported: [= boolean abbrev expression
|
||||
98 | a [= 1:2];
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:7: Unsupported: [= boolean abbrev expression
|
||||
94 | a [= 1:2];
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:98:10: Unsupported: boolean abbrev (in sequence expression)
|
||||
98 | a [= 1:2];
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:10: Unsupported: boolean abbrev (in sequence expression)
|
||||
94 | a [= 1:2];
|
||||
| ^
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:104:7: Unsupported: [-> range goto repetition
|
||||
104 | a [-> 1:2];
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:7: Unsupported: [-> range goto repetition
|
||||
100 | a [-> 1:2];
|
||||
| ^~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:107:26: Unsupported: sequence argument data type
|
||||
107 | sequence p_arg_seqence(sequence inseq);
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:26: Unsupported: sequence argument data type
|
||||
103 | sequence p_arg_seqence(sequence inseq);
|
||||
| ^~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:112:5: Unsupported: first_match (in sequence expression)
|
||||
112 | first_match (a);
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:108:5: Unsupported: first_match (in sequence expression)
|
||||
108 | first_match (a);
|
||||
| ^~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:115:5: Unsupported: first_match (in sequence expression)
|
||||
115 | first_match (a, res0 = 1);
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:111:5: Unsupported: first_match (in sequence expression)
|
||||
111 | first_match (a, res0 = 1);
|
||||
| ^~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:118:5: Unsupported: first_match (in sequence expression)
|
||||
118 | first_match (a, res0 = 1, res1 = 2);
|
||||
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:114:5: Unsupported: first_match (in sequence expression)
|
||||
114 | first_match (a, res0 = 1, res1 = 2);
|
||||
| ^~~~~~~~~~~
|
||||
%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:121:9: Ignoring unsupported: cover sequence
|
||||
121 | cover sequence (s_a) $display("");
|
||||
%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:117:9: Ignoring unsupported: cover sequence
|
||||
117 | cover sequence (s_a) $display("");
|
||||
| ^~~~~~~~
|
||||
... For warning description see https://verilator.org/warn/COVERIGN?v=latest
|
||||
... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message.
|
||||
%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:122:9: Ignoring unsupported: cover sequence
|
||||
122 | cover sequence (@(posedge a) disable iff (b) s_a) $display("");
|
||||
%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:118:9: Ignoring unsupported: cover sequence
|
||||
118 | cover sequence (@(posedge a) disable iff (b) s_a) $display("");
|
||||
| ^~~~~~~~
|
||||
%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:123:9: Ignoring unsupported: cover sequence
|
||||
123 | cover sequence (disable iff (b) s_a) $display("");
|
||||
%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:119:9: Ignoring unsupported: cover sequence
|
||||
119 | cover sequence (disable iff (b) s_a) $display("");
|
||||
| ^~~~~~~~
|
||||
%Error: Exiting due to
|
||||
|
|
|
|||
|
|
@ -42,10 +42,6 @@ module t (
|
|||
a or b;
|
||||
endsequence
|
||||
|
||||
sequence s_throughout;
|
||||
a throughout b;
|
||||
endsequence
|
||||
|
||||
sequence s_intersect;
|
||||
a intersect b;
|
||||
endsequence
|
||||
|
|
|
|||
Loading…
Reference in New Issue