From cd42b02a8f7bd3bde3016b5eab27323d316e333f Mon Sep 17 00:00:00 2001 From: Yilou Wang Date: Sun, 5 Apr 2026 09:43:23 +0200 Subject: [PATCH] Support sequence throughout operator --- src/V3AssertPre.cpp | 67 ++++++++++++-- src/V3AssertProp.cpp | 73 ++++++++++++++++ src/V3AstNodeExpr.h | 15 ++++ src/V3AstNodeStmt.h | 1 + src/V3EmitV.cpp | 5 ++ src/V3Width.cpp | 18 ++++ src/verilog.y | 2 +- test_regress/t/t_sequence_sexpr_throughout.py | 18 ++++ test_regress/t/t_sequence_sexpr_throughout.v | 67 ++++++++++++++ .../t/t_sequence_sexpr_throughout_unsup.out | 10 +++ .../t/t_sequence_sexpr_throughout_unsup.py | 18 ++++ .../t/t_sequence_sexpr_throughout_unsup.v | 20 +++++ test_regress/t/t_sequence_sexpr_unsup.out | 87 +++++++++---------- test_regress/t/t_sequence_sexpr_unsup.v | 4 - 14 files changed, 348 insertions(+), 57 deletions(-) create mode 100644 test_regress/t/t_sequence_sexpr_throughout.py create mode 100644 test_regress/t/t_sequence_sexpr_throughout.v create mode 100644 test_regress/t/t_sequence_sexpr_throughout_unsup.out create mode 100644 test_regress/t/t_sequence_sexpr_throughout_unsup.py create mode 100644 test_regress/t/t_sequence_sexpr_throughout_unsup.v diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp index 1417a8460..869153a4d 100644 --- a/src/V3AssertPre.cpp +++ b/src/V3AssertPre.cpp @@ -474,6 +474,9 @@ private: AstEventControl* const controlp = new AstEventControl{ nodep->fileline(), new AstSenTree{flp, sensesp->cloneTree(false)}, nullptr}; const std::string delayName = m_cycleDlyNames.get(nodep); + AstNodeExpr* throughoutp + = nodep->throughoutp() ? nodep->throughoutp()->unlinkFrBack() : nullptr; + AstVar* const cntVarp = new AstVar{flp, VVarType::BLOCKTEMP, delayName + "__counter", nodep->findBasicDType(VBasicDTypeKwd::UINT32)}; cntVarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); @@ -481,24 +484,74 @@ private: AstBegin* const beginp = new AstBegin{flp, delayName + "__block", cntVarp, true}; beginp->addStmtsp(new AstAssign{flp, new AstVarRef{flp, cntVarp, VAccess::WRITE}, valuep}); + // Throughout: create flag tracking whether condition held every tick + AstVar* throughoutOkp = nullptr; + if (throughoutp) { + throughoutOkp + = new AstVar{flp, VVarType::BLOCKTEMP, delayName + "__throughoutOk", + nodep->findBasicDType(VBasicDTypeKwd::LOGIC_IMPLICIT)}; + throughoutOkp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); + beginp->addStmtsp(throughoutOkp); + beginp->addStmtsp( + new AstAssign{flp, new AstVarRef{flp, throughoutOkp, VAccess::WRITE}, + new AstConst{flp, AstConst::BitTrue{}}}); + // Check condition at tick 0 (sequence start, before entering loop) + AstSampled* const initSampledp + = new AstSampled{flp, throughoutp->cloneTreePure(false)}; + initSampledp->dtypeSetBit(); + beginp->addStmtsp( + new AstIf{flp, new AstLogNot{flp, initSampledp}, + new AstAssign{flp, new AstVarRef{flp, throughoutOkp, VAccess::WRITE}, + new AstConst{flp, AstConst::BitFalse{}}}}); + } + { AstLoop* const loopp = new AstLoop{flp}; - loopp->addStmtsp(new AstLoopTest{ - flp, loopp, - new AstGt{flp, new AstVarRef{flp, cntVarp, VAccess::READ}, new AstConst{flp, 0}}}); + // When throughout is present, exit loop early if condition fails + AstNodeExpr* loopCondp + = new AstGt{flp, new AstVarRef{flp, cntVarp, VAccess::READ}, new AstConst{flp, 0}}; + if (throughoutOkp) { + loopCondp = new AstLogAnd{flp, loopCondp, + new AstVarRef{flp, throughoutOkp, VAccess::READ}}; + } + loopp->addStmtsp(new AstLoopTest{flp, loopp, loopCondp}); loopp->addStmtsp(controlp); loopp->addStmtsp( new AstAssign{flp, new AstVarRef{flp, cntVarp, VAccess::WRITE}, new AstSub{flp, new AstVarRef{flp, cntVarp, VAccess::READ}, new AstConst{flp, 1}}}); + // Check throughout condition at each tick during delay (IEEE 1800-2023 16.9.9) + if (throughoutp) { + AstSampled* const sampledp = new AstSampled{flp, throughoutp}; + sampledp->dtypeSetBit(); + loopp->addStmtsp( + new AstIf{flp, new AstLogNot{flp, sampledp}, + new AstAssign{flp, + new AstVarRef{flp, throughoutOkp, VAccess::WRITE}, + new AstConst{flp, AstConst::BitFalse{}}}}); + } beginp->addStmtsp(loopp); } - if (m_disableSeqIfp) { + // Compose wrappers on remaining sequence: throughout gate (inner), disable iff (outer) + AstNode* remainp = nodep->nextp() ? nodep->nextp()->unlinkFrBackWithNext() : nullptr; + if (throughoutOkp) { + // If condition failed during delay, fail assertion + remainp = new AstIf{flp, new AstVarRef{flp, throughoutOkp, VAccess::READ}, remainp, + new AstPExprClause{flp, /*pass=*/false}}; + } + if (m_disableSeqIfp && remainp) { AstIf* const disableSeqIfp = m_disableSeqIfp->cloneTree(false); - AstNode* const continuationsp = nodep->nextp()->unlinkFrBackWithNext(); // Keep continuation statements in a proper statement-list container. - disableSeqIfp->addThensp(new AstBegin{flp, "", continuationsp, true}); - nodep->addNextHere(disableSeqIfp); + disableSeqIfp->addThensp(new AstBegin{flp, "", remainp, true}); + remainp = disableSeqIfp; + } + if (remainp) { + if (throughoutOkp) { + // throughoutOkp is declared in beginp scope -- check must be inside it + beginp->addStmtsp(remainp); + } else { + nodep->addNextHere(remainp); + } } nodep->replaceWith(beginp); VL_DO_DANGLING(nodep->deleteTree(), nodep); diff --git a/src/V3AssertProp.cpp b/src/V3AssertProp.cpp index 6888284c4..e14d6af7b 100644 --- a/src/V3AssertProp.cpp +++ b/src/V3AssertProp.cpp @@ -422,6 +422,45 @@ class AssertPropLowerVisitor final : public VNVisitor { VL_DO_DANGLING(nodep->deleteTree(), nodep); } } + void visit(AstSExprThroughout* nodep) override { + // IEEE 1800-2023 16.9.9: expr throughout seq + // Transform by AND-ing cond with every leaf expression in the sequence, + // and attaching cond to every delay for per-tick checking in V3AssertPre. + AstNodeExpr* const condp = nodep->condp()->unlinkFrBack(); + AstNodeExpr* const seqp = nodep->seqp()->unlinkFrBack(); + if (AstSExpr* const sexprp = VN_CAST(seqp, SExpr)) { + // Walk all SExpr nodes: AND cond with leaf expressions, attach to delays + sexprp->foreach([&](AstSExpr* sp) { + if (sp->exprp() && !VN_IS(sp->exprp(), SExpr)) { + AstNodeExpr* const origp = sp->exprp()->unlinkFrBack(); + AstLogAnd* const andp + = new AstLogAnd{origp->fileline(), condp->cloneTreePure(false), origp}; + andp->dtypeSetBit(); + sp->exprp(andp); + } + if (sp->preExprp() && !VN_IS(sp->preExprp(), SExpr)) { + AstNodeExpr* const origp = sp->preExprp()->unlinkFrBack(); + AstLogAnd* const andp + = new AstLogAnd{origp->fileline(), condp->cloneTreePure(false), origp}; + andp->dtypeSetBit(); + sp->preExprp(andp); + } + if (AstDelay* const dlyp = VN_CAST(sp->delayp(), Delay)) { + dlyp->throughoutp(condp->cloneTreePure(false)); + } + }); + nodep->replaceWith(sexprp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + VL_DO_DANGLING(condp->deleteTree(), condp); + visit(sexprp); + } else { + // Single expression (no delay): degenerate to cond && seq + AstLogAnd* const andp = new AstLogAnd{nodep->fileline(), condp, seqp}; + andp->dtypeSetBit(); + nodep->replaceWith(andp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + } + } void visit(AstNodeModule* nodep) override { VL_RESTORER(m_modp); m_modp = nodep; @@ -982,6 +1021,40 @@ class RangeDelayExpander final : public VNVisitor { } } + void visit(AstSExprThroughout* nodep) override { + // Reject throughout with range-delay sequences before FSM expansion + // would silently lose per-tick enforcement (IEEE 1800-2023 16.9.9) + if (AstSExpr* const sexprp = VN_CAST(nodep->seqp(), SExpr)) { + if (containsRangeDelay(sexprp)) { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: throughout with range delay sequence"); + nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}}); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + return; + } + } + // Reject throughout with nested throughout or goto repetition + if (VN_IS(nodep->seqp(), SExprThroughout) || VN_IS(nodep->seqp(), SExprGotoRep)) { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: throughout with complex sequence operator"); + nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}}); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + return; + } + // Reject throughout with temporal SAnd/SOr (containing SExpr = multi-cycle). + // Pure boolean SAnd/SOr are OK -- AssertPropLowerVisitor lowers them to LogAnd/LogOr. + if (VN_IS(nodep->seqp(), SAnd) || VN_IS(nodep->seqp(), SOr)) { + bool hasSExpr = false; + nodep->seqp()->foreach([&](const AstSExpr*) { hasSExpr = true; }); + if (hasSExpr) { + nodep->v3warn(E_UNSUPPORTED, + "Unsupported: throughout with complex sequence operator"); + nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}}); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + return; + } + } + iterateChildren(nodep); + } + void visit(AstNode* nodep) override { iterateChildren(nodep); } public: diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index eeaf92f86..708f85fd6 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -2181,6 +2181,21 @@ public: string emitC() override { V3ERROR_NA_RETURN(""); } bool cleanOut() const override { V3ERROR_NA_RETURN(""); } }; +class AstSExprThroughout final : public AstNodeExpr { + // expr throughout seq (IEEE 1800-2023 16.9.9) + // @astgen op1 := condp : AstNodeExpr // Boolean LHS + // @astgen op2 := seqp : AstNodeExpr // Sequence RHS +public: + AstSExprThroughout(FileLine* fl, AstNodeExpr* condp, AstNodeExpr* seqp) + : ASTGEN_SUPER_SExprThroughout(fl) { + this->condp(condp); + this->seqp(seqp); + } + ASTGEN_MEMBERS_AstSExprThroughout; + string emitVerilog() override { V3ERROR_NA_RETURN(""); } + string emitC() override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const override { V3ERROR_NA_RETURN(""); } +}; class AstSFormatArg final : public AstNodeExpr { // Information for formatting each argument to AstSFormat, // used to pass to (potentially) runtime decoding of format arguments diff --git a/src/V3AstNodeStmt.h b/src/V3AstNodeStmt.h index 5a332599c..d18e7d88f 100644 --- a/src/V3AstNodeStmt.h +++ b/src/V3AstNodeStmt.h @@ -544,6 +544,7 @@ class AstDelay final : public AstNodeStmt { // @astgen op1 := lhsp : AstNodeExpr // Delay value (or min for range) // @astgen op2 := stmtsp : List[AstNode] // Statements under delay // @astgen op3 := rhsp : Optional[AstNodeExpr] // Max delay value (range delay only) + // @astgen op4 := throughoutp : Optional[AstNodeExpr] // Throughout condition (IEEE 16.9.9) VTimescale m_timeunit; // Delay's time unit const bool m_isCycle; // True if it is a cycle delay diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index 0272c62db..05768d448 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -1067,6 +1067,11 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst { } iterateConst(nodep->exprp()); } + void visit(AstSExprThroughout* nodep) override { + iterateConst(nodep->condp()); + puts(" throughout "); + iterateConst(nodep->seqp()); + } // Terminals void visit(AstVarRef* nodep) override { diff --git a/src/V3Width.cpp b/src/V3Width.cpp index c0b25f1c8..b614e15e2 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -1645,6 +1645,24 @@ class WidthVisitor final : public VNVisitor { nodep->dtypeSetBit(); } } + void visit(AstSExprThroughout* nodep) override { + m_hasSExpr = true; + assertAtExpr(nodep); + if (m_vup->prelim()) { + // condp is a boolean expression, not a sequence -- clear m_underSExpr + { + VL_RESTORER(m_underSExpr); + m_underSExpr = false; + iterateCheckBool(nodep, "condp", nodep->condp(), BOTH); + } + { + VL_RESTORER(m_underSExpr); + m_underSExpr = true; + iterate(nodep->seqp()); + } + nodep->dtypeSetBit(); + } + } void visit(AstSExpr* nodep) override { VL_RESTORER(m_underSExpr); m_underSExpr = true; diff --git a/src/verilog.y b/src/verilog.y index 2585fdc11..f896ab059 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -6849,7 +6849,7 @@ sexpr: // ==IEEE: sequence_expr (The name sexpr is important as reg | yFIRST_MATCH '(' sexpr ',' sequence_match_itemList ')' { $$ = $3; BBUNSUP($1, "Unsupported: first_match (in sequence expression)"); DEL($5); } | ~p~sexpr/*sexpression_or_dist*/ yTHROUGHOUT sexpr - { $$ = $1; BBUNSUP($2, "Unsupported: throughout (in sequence expression)"); DEL($3); } + { $$ = new AstSExprThroughout{$2, $1, $3}; } // // Below pexpr's are really sequence_expr, but avoid conflict // // IEEE: sexpr yWITHIN sexpr | ~p~sexpr yWITHIN sexpr diff --git a/test_regress/t/t_sequence_sexpr_throughout.py b/test_regress/t/t_sequence_sexpr_throughout.py new file mode 100644 index 000000000..35e44000c --- /dev/null +++ b/test_regress/t/t_sequence_sexpr_throughout.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sequence_sexpr_throughout.v b/test_regress/t/t_sequence_sexpr_throughout.v new file mode 100644 index 000000000..f47b51685 --- /dev/null +++ b/test_regress/t/t_sequence_sexpr_throughout.v @@ -0,0 +1,67 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +// IEEE 1800-2023 16.9.9: expr throughout seq +// CRC-driven random stimulus exercises throughout with varying cond/a/b signals. + +module t ( + input clk +); + integer cyc = 0; + reg [63:0] crc = '0; + + // Derive signals from non-adjacent CRC bits (gap > max delay to avoid LFSR correlation) + wire cond = crc[0]; + wire a = crc[4]; + wire b = crc[8]; + + int count_fail1 = 0; + int count_fail2 = 0; + int count_fail3 = 0; + + // Test 1: a |-> (cond throughout (1'b1 ##3 1'b1)) + // If a fires, cond must hold for 4 consecutive ticks (start + 3 delay ticks). + assert property (@(posedge clk) disable iff (cyc < 10) + a |-> (cond throughout (1'b1 ##3 1'b1))) + else count_fail1 <= count_fail1 + 1; + + // Test 2: a |-> (cond throughout (1'b1 ##1 b)) + // If a fires, cond must hold for 2 ticks and b must be true at tick +1. + assert property (@(posedge clk) disable iff (cyc < 10) + a |-> (cond throughout (1'b1 ##1 b))) + else count_fail2 <= count_fail2 + 1; + + // Test 3: a |-> (cond throughout b) + // No delay: degenerates to a |-> (cond && b). + assert property (@(posedge clk) disable iff (cyc < 10) + a |-> (cond throughout b)) + else count_fail3 <= count_fail3 + 1; + + always_ff @(posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x cond=%b a=%b b=%b\n", + $time, cyc, crc, cond, a, b); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + crc <= 64'h5aef0c8d_d70a4497; + end else if (cyc == 99) begin + `checkh(crc, 64'hc77bb9b3784ea091); + `checkd(count_fail1, 36); + `checkd(count_fail2, 37); + `checkd(count_fail3, 31); + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_sequence_sexpr_throughout_unsup.out b/test_regress/t/t_sequence_sexpr_throughout_unsup.out new file mode 100644 index 000000000..8497ca370 --- /dev/null +++ b/test_regress/t/t_sequence_sexpr_throughout_unsup.out @@ -0,0 +1,10 @@ +%Error-UNSUPPORTED: t/t_sequence_sexpr_throughout_unsup.v:14:16: Unsupported: throughout with range delay sequence + : ... note: In instance 't' + 14 | a |-> (a throughout (b ##[1:2] c))); + | ^~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_sequence_sexpr_throughout_unsup.v:18:16: Unsupported: throughout with complex sequence operator + : ... note: In instance 't' + 18 | a |-> (a throughout ((b ##1 c) and (c ##1 b)))); + | ^~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_sequence_sexpr_throughout_unsup.py b/test_regress/t/t_sequence_sexpr_throughout_unsup.py new file mode 100644 index 000000000..1c3e73246 --- /dev/null +++ b/test_regress/t/t_sequence_sexpr_throughout_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, + verilator_flags2=['--assert --timing --error-limit 1000'], + fails=True) + +test.passes() diff --git a/test_regress/t/t_sequence_sexpr_throughout_unsup.v b/test_regress/t/t_sequence_sexpr_throughout_unsup.v new file mode 100644 index 000000000..a114feabd --- /dev/null +++ b/test_regress/t/t_sequence_sexpr_throughout_unsup.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input clk +); + logic a, b, c; + + // Unsupported: throughout with range delay on RHS (IEEE 16.9.9) + assert property (@(posedge clk) + a |-> (a throughout (b ##[1:2] c))); + + // Unsupported: throughout with temporal 'and' sequence on RHS + assert property (@(posedge clk) + a |-> (a throughout ((b ##1 c) and (c ##1 b)))); + +endmodule diff --git a/test_regress/t/t_sequence_sexpr_unsup.out b/test_regress/t/t_sequence_sexpr_unsup.out index e97f8e521..ca728f106 100644 --- a/test_regress/t/t_sequence_sexpr_unsup.out +++ b/test_regress/t/t_sequence_sexpr_unsup.out @@ -2,72 +2,69 @@ 34 | a within(b); | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:46:7: Unsupported: throughout (in sequence expression) - 46 | a throughout b; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:50:7: Unsupported: intersect (in sequence expression) - 50 | a intersect b; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:46:7: Unsupported: intersect (in sequence expression) + 46 | a intersect b; | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:63:5: Unsupported: ## [*] cycle delay range expression - 63 | ## [*] b; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:59:5: Unsupported: ## [*] cycle delay range expression + 59 | ## [*] b; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:66:5: Unsupported: ## [+] cycle delay range expression - 66 | ## [+] b; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:62:5: Unsupported: ## [+] cycle delay range expression + 62 | ## [+] b; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:79:7: Unsupported: ## [*] cycle delay range expression - 79 | a ## [*] b; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:75:7: Unsupported: ## [*] cycle delay range expression + 75 | a ## [*] b; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:82:7: Unsupported: ## [+] cycle delay range expression - 82 | a ## [+] b; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:78:7: Unsupported: ## [+] cycle delay range expression + 78 | a ## [+] b; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:89:7: Unsupported: [*] boolean abbrev expression - 89 | a [*]; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:85:7: Unsupported: [*] boolean abbrev expression + 85 | a [*]; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:89:7: Unsupported: boolean abbrev (in sequence expression) - 89 | a [*]; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:85:7: Unsupported: boolean abbrev (in sequence expression) + 85 | a [*]; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:92:7: Unsupported: [+] boolean abbrev expression - 92 | a [+]; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:88:7: Unsupported: [+] boolean abbrev expression + 88 | a [+]; | ^~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:92:7: Unsupported: boolean abbrev (in sequence expression) - 92 | a [+]; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:88:7: Unsupported: boolean abbrev (in sequence expression) + 88 | a [+]; | ^~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:95:7: Unsupported: [= boolean abbrev expression - 95 | a [= 1]; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:7: Unsupported: [= boolean abbrev expression + 91 | a [= 1]; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:95:10: Unsupported: boolean abbrev (in sequence expression) - 95 | a [= 1]; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:10: Unsupported: boolean abbrev (in sequence expression) + 91 | a [= 1]; | ^ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:98:7: Unsupported: [= boolean abbrev expression - 98 | a [= 1:2]; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:7: Unsupported: [= boolean abbrev expression + 94 | a [= 1:2]; | ^~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:98:10: Unsupported: boolean abbrev (in sequence expression) - 98 | a [= 1:2]; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:10: Unsupported: boolean abbrev (in sequence expression) + 94 | a [= 1:2]; | ^ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:104:7: Unsupported: [-> range goto repetition - 104 | a [-> 1:2]; +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:7: Unsupported: [-> range goto repetition + 100 | a [-> 1:2]; | ^~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:107:26: Unsupported: sequence argument data type - 107 | sequence p_arg_seqence(sequence inseq); +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:26: Unsupported: sequence argument data type + 103 | sequence p_arg_seqence(sequence inseq); | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:112:5: Unsupported: first_match (in sequence expression) - 112 | first_match (a); +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:108:5: Unsupported: first_match (in sequence expression) + 108 | first_match (a); | ^~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:115:5: Unsupported: first_match (in sequence expression) - 115 | first_match (a, res0 = 1); +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:111:5: Unsupported: first_match (in sequence expression) + 111 | first_match (a, res0 = 1); | ^~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:118:5: Unsupported: first_match (in sequence expression) - 118 | first_match (a, res0 = 1, res1 = 2); +%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:114:5: Unsupported: first_match (in sequence expression) + 114 | first_match (a, res0 = 1, res1 = 2); | ^~~~~~~~~~~ -%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:121:9: Ignoring unsupported: cover sequence - 121 | cover sequence (s_a) $display(""); +%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:117:9: Ignoring unsupported: cover sequence + 117 | cover sequence (s_a) $display(""); | ^~~~~~~~ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. -%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:122:9: Ignoring unsupported: cover sequence - 122 | cover sequence (@(posedge a) disable iff (b) s_a) $display(""); +%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:118:9: Ignoring unsupported: cover sequence + 118 | cover sequence (@(posedge a) disable iff (b) s_a) $display(""); | ^~~~~~~~ -%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:123:9: Ignoring unsupported: cover sequence - 123 | cover sequence (disable iff (b) s_a) $display(""); +%Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:119:9: Ignoring unsupported: cover sequence + 119 | cover sequence (disable iff (b) s_a) $display(""); | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_sequence_sexpr_unsup.v b/test_regress/t/t_sequence_sexpr_unsup.v index eac565574..b8185f1ea 100644 --- a/test_regress/t/t_sequence_sexpr_unsup.v +++ b/test_regress/t/t_sequence_sexpr_unsup.v @@ -42,10 +42,6 @@ module t ( a or b; endsequence - sequence s_throughout; - a throughout b; - endsequence - sequence s_intersect; a intersect b; endsequence