Test: Added a two-dimensional parameter test

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Greg Davill 2026-04-10 22:16:57 +09:30
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commit cc2b83c04d
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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.execute()
test.passes()

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2020 Dustin Richmond
// SPDX-License-Identifier: CC0-1.0
// Test: 2D array parameter passed to sub-modules via generate loops
module baz
#(
parameter integer type_p = '0
)
();
endmodule
module t
#(
parameter integer n_x_p = 4
,parameter integer n_y_p = 4
,parameter integer twodim_p [0:n_y_p-1][0:n_x_p-1] = '{n_y_p{'{n_x_p{0}}}}
)
();
genvar r, c;
for (r = 0; r < n_y_p; r = r+1)
begin: y
for (c = 0; c < n_x_p; c=c+1)
begin: x
baz
#(.type_p(twodim_p[r][c]))
baz_i
();
end
end
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule