Tests: Add tests for multi-dimensional array localparam pattern initialisation

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Greg Davill 2026-04-10 08:58:01 +09:30
parent 57ce373e99
commit ad3e38313d
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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.execute()
test.passes()

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 Greg Davill
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,
expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t ( /*AUTOARG*/);
// Test: 2D array localparam with pattern initialization
localparam logic [31:0] MATRIX[2][3] = '{'{32'hA0, 32'hA1, 32'hA2}, '{32'hB0, 32'hB1, 32'hB2}};
// Deriving a localparam from a 2D array element
localparam logic [31:0] DERIVED_A0 = MATRIX[0][0];
localparam logic [31:0] DERIVED_B2 = MATRIX[1][2];
// Use derived values as sub-module parameters to force elaboration-time resolution
sub #(.VAL(MATRIX[0][1])) u_sub ();
initial begin
`checkh(DERIVED_A0, 32'hA0);
`checkh(DERIVED_B2, 32'hB2);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub #(
parameter logic [31:0] VAL = 0
) ();
initial begin
if (VAL !== 32'hA1) begin
$display("%%Error: sub VAL='h%x expected 'hA1", VAL);
$stop;
end
end
endmodule

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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.execute()
test.passes()

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 Greg Davill
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,
expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t ( /*AUTOARG*/);
// Test: 3D array localparam with pattern initialization
localparam logic [31:0] CUBE[2][2][2] = '{
'{'{32'h00, 32'h01}, '{32'h10, 32'h11}},
'{'{32'h20, 32'h21}, '{32'h30, 32'h31}}
};
// Deriving a localparam from a 3D array element
localparam logic [31:0] CUBE_VAL = CUBE[1][0][1];
initial begin
`checkh(CUBE_VAL, 32'h21);
`checkh(CUBE[0][0][0], 32'h00);
`checkh(CUBE[0][1][1], 32'h11);
`checkh(CUBE[1][1][0], 32'h30);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule