From c970743b07b30def52f12d98c917b0162c745f7f Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 20 Feb 2026 18:54:36 -0500 Subject: [PATCH] Tests: Renames. No test change. --- test_regress/t/t_sys_rand.v | 37 ---------- test_regress/t/t_sys_rand_concat.v | 60 ---------------- test_regress/t/t_sys_rand_seed.v | 70 ------------------- .../t/{t_sys_rand.py => t_sys_random.py} | 0 test_regress/t/t_sys_random.v | 37 ++++++++++ ..._rand_concat.py => t_sys_random_concat.py} | 0 test_regress/t/t_sys_random_concat.v | 62 ++++++++++++++++ ..._sys_rand_seed.py => t_sys_random_seed.py} | 0 test_regress/t/t_sys_random_seed.v | 70 +++++++++++++++++++ ...random.py => t_x_rand_scoped_is_random.py} | 0 ...s_random.v => t_x_rand_scoped_is_random.v} | 0 11 files changed, 169 insertions(+), 167 deletions(-) delete mode 100644 test_regress/t/t_sys_rand.v delete mode 100644 test_regress/t/t_sys_rand_concat.v delete mode 100644 test_regress/t/t_sys_rand_seed.v rename test_regress/t/{t_sys_rand.py => t_sys_random.py} (100%) create mode 100644 test_regress/t/t_sys_random.v rename test_regress/t/{t_sys_rand_concat.py => t_sys_random_concat.py} (100%) create mode 100644 test_regress/t/t_sys_random_concat.v rename test_regress/t/{t_sys_rand_seed.py => t_sys_random_seed.py} (100%) create mode 100644 test_regress/t/t_sys_random_seed.v rename test_regress/t/{t_scoped_rand_is_random.py => t_x_rand_scoped_is_random.py} (100%) rename test_regress/t/{t_scoped_rand_is_random.v => t_x_rand_scoped_is_random.v} (100%) diff --git a/test_regress/t/t_sys_rand.v b/test_regress/t/t_sys_rand.v deleted file mode 100644 index 3db50bf25..000000000 --- a/test_regress/t/t_sys_rand.v +++ /dev/null @@ -1,37 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2008 Wilson Snyder -// SPDX-License-Identifier: CC0-1.0 - -module t; - - reg [31:0] lastrand; - reg [31:0] thisrand; - - integer same = 0; - integer i; - -`define TRIES 20 - - initial begin - // There's a 1^32 chance of the numbers being the same twice, - // so we'll allow one failure - lastrand = $random; - for (i=0; i<`TRIES; i=i+1) begin - thisrand = $random; -`ifdef TEST_VERBOSE - $write("Random = %x\n", thisrand); -`endif - if (thisrand == lastrand) same=same+1; - lastrand = thisrand; - end - if (same > 1) begin - $write("%%Error: Too many similar numbers: %d\n", same); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_sys_rand_concat.v b/test_regress/t/t_sys_rand_concat.v deleted file mode 100644 index 8f50d6dd5..000000000 --- a/test_regress/t/t_sys_rand_concat.v +++ /dev/null @@ -1,60 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2008 Wilson Snyder -// SPDX-License-Identifier: CC0-1.0 - -`define stop $stop -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) - -module t; - -`define TRIES 100 - - bit [6:0] b5a; // We use larger than [4:0] so make sure we truncate - bit [6:0] b5b; // We use larger than [4:0] so make sure we truncate - bit [6:0] b7c; - bit [6:0] b7d; - bit [59:0] b60c; - bit [89:0] b90c; - - bit [6:0] max_b5a; - bit [6:0] max_b5b; - bit [6:0] max_b7c; - bit [6:0] max_b7d; - bit [59:0] max_b60c; - bit [89:0] max_b90c; - - initial begin - for (int i = 0; i < `TRIES; ++i) begin - // verilator lint_off WIDTH - // Optimize away extracts - b5a = {$random}[4:0]; - b5b = {$random}[14:10]; - // Optimize away concats - b7c = {$random, $random, $random, $random, $random, $random, $random}; - b7d = {{{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}}; - b60c = {$random, $random, $random, $random, $random, $random, $random}; - b90c = {$random, $random, $random, $random, $random, $random, $random}; - // verilator lint_on WIDTH - - max_b5a = max_b5a | b5a; - max_b5b = max_b5b | b5b; - max_b7c = max_b7c | b7c; - max_b7d = max_b7d | b7d; - max_b60c = max_b60c | b60c; - max_b90c = max_b90c | b90c; - end - - `checkh(max_b5a, 7'h1f); - `checkh(max_b5b, 7'h1f); - `checkh(max_b7c, 7'h7f); - `checkh(max_b7d, 7'h1f); - `checkh(max_b60c, ~ 60'h0); - `checkh(max_b90c, ~ 90'h0); - - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_sys_rand_seed.v b/test_regress/t/t_sys_rand_seed.v deleted file mode 100644 index ad492610e..000000000 --- a/test_regress/t/t_sys_rand_seed.v +++ /dev/null @@ -1,70 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2020 Wilson Snyder -// SPDX-License-Identifier: CC0-1.0 - -module t; - - integer seeda; - integer seedb; - integer seedc; - int valuea; - int valueb; - int valuec; - int igna; - int ignb; - int ignc; - - initial begin - // $random unlike $urandom updates the value if given - seeda = 10; - valuea = $random(seeda); - seedb = 10; - valueb = $random(seedb); - if (valuea !== valueb) $stop; - - seeda = 10; - valuea = $random(seeda); - seedb = seeda; - valueb = $random(seedb); - seedc = seedb; - valuec = $random(seedc); - if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 - if (seeda == seedb && seedb == seedc) $stop; // May false fail 1 in 1^64 - - valuea = $urandom(10); - valueb = $urandom(10); - valuec = $urandom(10); - if (valuea !== valueb && valueb != valuec) $stop; - - valuea = $urandom(10); - valueb = $urandom(11); - valuec = $urandom(12); - if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 - - $urandom(10); - valuea = $urandom; - $urandom(10); - valueb = $urandom; - $urandom(10); - valuec = $urandom; - if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64 - - igna = $urandom(10); - valuea = $urandom; - ignb = $urandom(10); - valueb = $urandom; - ignc = $urandom(10); - valuec = $urandom; - if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64 - - valuea = $urandom(10); - valueb = $urandom(); - valuec = $urandom(); - if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 - - $write("*-* All Finished *-*\n"); - $finish; - end -endmodule diff --git a/test_regress/t/t_sys_rand.py b/test_regress/t/t_sys_random.py similarity index 100% rename from test_regress/t/t_sys_rand.py rename to test_regress/t/t_sys_random.py diff --git a/test_regress/t/t_sys_random.v b/test_regress/t/t_sys_random.v new file mode 100644 index 000000000..93930b7b2 --- /dev/null +++ b/test_regress/t/t_sys_random.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + + reg [31:0] lastrand; + reg [31:0] thisrand; + + integer same = 0; + integer i; + + `define TRIES 20 + + initial begin + // There's a 1^32 chance of the numbers being the same twice, + // so we'll allow one failure + lastrand = $random; + for (i = 0; i < `TRIES; i = i + 1) begin + thisrand = $random; +`ifdef TEST_VERBOSE + $write("Random = %x\n", thisrand); +`endif + if (thisrand == lastrand) same = same + 1; + lastrand = thisrand; + end + if (same > 1) begin + $write("%%Error: Too many similar numbers: %d\n", same); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_sys_rand_concat.py b/test_regress/t/t_sys_random_concat.py similarity index 100% rename from test_regress/t/t_sys_rand_concat.py rename to test_regress/t/t_sys_random_concat.py diff --git a/test_regress/t/t_sys_random_concat.v b/test_regress/t/t_sys_random_concat.v new file mode 100644 index 000000000..e414613e3 --- /dev/null +++ b/test_regress/t/t_sys_random_concat.v @@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on + +module t; + + `define TRIES 100 + + bit [6:0] b5a; // We use larger than [4:0] so make sure we truncate + bit [6:0] b5b; // We use larger than [4:0] so make sure we truncate + bit [6:0] b7c; + bit [6:0] b7d; + bit [59:0] b60c; + bit [89:0] b90c; + + bit [6:0] max_b5a; + bit [6:0] max_b5b; + bit [6:0] max_b7c; + bit [6:0] max_b7d; + bit [59:0] max_b60c; + bit [89:0] max_b90c; + + initial begin + for (int i = 0; i < `TRIES; ++i) begin + // verilator lint_off WIDTH + // Optimize away extracts + b5a = {$random}[4:0]; + b5b = {$random}[14:10]; + // Optimize away concats + b7c = {$random, $random, $random, $random, $random, $random, $random}; + b7d = {{{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}}; + b60c = {$random, $random, $random, $random, $random, $random, $random}; + b90c = {$random, $random, $random, $random, $random, $random, $random}; + // verilator lint_on WIDTH + + max_b5a = max_b5a | b5a; + max_b5b = max_b5b | b5b; + max_b7c = max_b7c | b7c; + max_b7d = max_b7d | b7d; + max_b60c = max_b60c | b60c; + max_b90c = max_b90c | b90c; + end + + `checkh(max_b5a, 7'h1f); + `checkh(max_b5b, 7'h1f); + `checkh(max_b7c, 7'h7f); + `checkh(max_b7d, 7'h1f); + `checkh(max_b60c, ~60'h0); + `checkh(max_b90c, ~90'h0); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_sys_rand_seed.py b/test_regress/t/t_sys_random_seed.py similarity index 100% rename from test_regress/t/t_sys_rand_seed.py rename to test_regress/t/t_sys_random_seed.py diff --git a/test_regress/t/t_sys_random_seed.v b/test_regress/t/t_sys_random_seed.v new file mode 100644 index 000000000..0342473e2 --- /dev/null +++ b/test_regress/t/t_sys_random_seed.v @@ -0,0 +1,70 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + + integer seeda; + integer seedb; + integer seedc; + int valuea; + int valueb; + int valuec; + int igna; + int ignb; + int ignc; + + initial begin + // $random unlike $urandom updates the value if given + seeda = 10; + valuea = $random(seeda); + seedb = 10; + valueb = $random(seedb); + if (valuea !== valueb) $stop; + + seeda = 10; + valuea = $random(seeda); + seedb = seeda; + valueb = $random(seedb); + seedc = seedb; + valuec = $random(seedc); + if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 + if (seeda == seedb && seedb == seedc) $stop; // May false fail 1 in 1^64 + + valuea = $urandom(10); + valueb = $urandom(10); + valuec = $urandom(10); + if (valuea !== valueb && valueb != valuec) $stop; + + valuea = $urandom(10); + valueb = $urandom(11); + valuec = $urandom(12); + if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 + + $urandom(10); + valuea = $urandom; + $urandom(10); + valueb = $urandom; + $urandom(10); + valuec = $urandom; + if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64 + + igna = $urandom(10); + valuea = $urandom; + ignb = $urandom(10); + valueb = $urandom; + ignc = $urandom(10); + valuec = $urandom; + if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64 + + valuea = $urandom(10); + valueb = $urandom(); + valuec = $urandom(); + if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_scoped_rand_is_random.py b/test_regress/t/t_x_rand_scoped_is_random.py similarity index 100% rename from test_regress/t/t_scoped_rand_is_random.py rename to test_regress/t/t_x_rand_scoped_is_random.py diff --git a/test_regress/t/t_scoped_rand_is_random.v b/test_regress/t/t_x_rand_scoped_is_random.v similarity index 100% rename from test_regress/t/t_scoped_rand_is_random.v rename to test_regress/t/t_x_rand_scoped_is_random.v