Tests: Reformat some tests to mostly verilog-format standard. No test functional change.

test_regress/t/t_interface_array_loop_bad.v

@@ -8,13 +8,10 @@ interface simple_bad_if;
   logic [7:0] value;
 endinterface
 
-module t (  /*AUTOARG*/
-    // Inputs
-    clk
+module t (
+    input clk
 );
 
-  input clk;
-
   localparam N = 4;
 
   simple_bad_if ifaces[N-1:0] ();