Tests: Upgrade some failing tests without expected .out files.
This commit is contained in:
Wilson Snyder
parent
8ac8c64885
commit
c73259d2f0
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%Error: t/t_const_slicesel_bad.v:12:42: Slice selection index '[3:1]' outside data type's '[2:0]'
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: ... note: In instance 't'
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12 | localparam int unsigned B32_T[1:0] = A3[3:1];
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| ^
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Exiting due to
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@ -12,6 +12,6 @@ import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=True)
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -28,12 +28,9 @@ for s in [
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'EOF in unterminated string', # Instead get normal unterminated
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'Enum ranges must be integral, per spec', # Hard to hit
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'Expecting define formal arguments. Found: ', # Instead define syntax error
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'Import package not found: ', # Errors earlier, until future parser released
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'Member selection of non-struct/union object \'', # Instead dotted expression error or V3Link other
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'Return with return value isn\'t underneath a function', # Hard to hit, get other bad return messages
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'Syntax error parsing real: \'', # Instead can't lex the number
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'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance ', # Instead get syntax error
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'Unsupported: Ranges ignored in port-lists', # Hard to hit
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'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error
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# Not yet analyzed
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'--pipe-filter protocol error, unexpected: ',
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@ -53,7 +50,6 @@ for s in [
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'Illegal +: or -: select; type already selected, or bad dimension: ',
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'Illegal bit or array select; type already selected, or bad dimension: ',
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'Illegal range select; type already selected, or bad dimension: ',
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'Interface port ',
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'Interface port declaration ',
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'Modport item is not a function/task: ',
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'Modport item is not a variable: ',
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@ -64,7 +60,6 @@ for s in [
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'Parameter type pin value isn\'t a type: Param ',
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'Parameter type variable isn\'t a type: Param ',
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'Pattern replication value of 0 is not legal.',
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'Reference to \'',
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'Signals inside functions/tasks cannot be marked forceable',
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'Slice size cannot be zero.',
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'Slices of arrays in assignments have different unpacked dimensions, ',
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@ -0,0 +1,3 @@
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%Error: Unknown language specified: 1-2-3-4
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Exiting due to
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@ -11,6 +11,8 @@ import vltest_bootstrap
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test.scenarios('vlt')
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test.lint(verilator_flags2=['--language 1-2-3-4'], fails=True)
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test.lint(verilator_flags2=['--language 1-2-3-4'],
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fails=True,
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expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,10 @@
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%Error: t/t_fuzz_eof_bad.v:3:31: Unterminated string
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: t/t_fuzz_eof_bad.v:2:21: EOF in (*
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2 | initial $lay(*Hello!=nendmodule
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| ^
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%Error: t/t_fuzz_eof_bad.v:2:21: syntax error, unexpected end of file
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2 | initial $lay(*Hello!=nendmodule
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| ^
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%Error: Cannot continue
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... This fatal error may be caused by the earlier error(s); resolve those first.
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@ -11,6 +11,6 @@ import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=True)
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,9 @@
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%Error: t/t_langext_1.v:44:7: syntax error, unexpected IDENTIFIER-for-type
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44 | genvar i;
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| ^~~~~~
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: t/t_langext_1.v:51:1: syntax error, unexpected endmodule, expecting '('
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51 | endmodule
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| ^~~~~~~~~
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%Error: Cannot continue
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... This fatal error may be caused by the earlier error(s); resolve those first.
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@ -13,6 +13,6 @@ test.scenarios('linter')
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test.top_filename = "t/t_langext_1.v"
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# This is a lint only test.
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test.lint(v_flags2=["+verilog1995ext+v"], fails=True)
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test.lint(v_flags2=["+verilog1995ext+v"], fails=True, expect_filename=test.golden_filename)
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test.passes()
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%Error: t/t_langext_1.v:44:7: syntax error, unexpected IDENTIFIER-for-type
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44 | genvar i;
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| ^~~~~~
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: t/t_langext_1.v:51:1: syntax error, unexpected endmodule, expecting '('
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51 | endmodule
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| ^~~~~~~~~
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%Error: Cannot continue
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... This fatal error may be caused by the earlier error(s); resolve those first.
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@ -13,6 +13,6 @@ test.scenarios('linter')
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test.top_filename = "t/t_langext_1.v"
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# This is a lint only test.
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test.lint(v_flags2=["+verilog1995ext+.v"], fails=True)
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test.lint(v_flags2=["+verilog1995ext+.v"], fails=True, expect_filename=test.golden_filename)
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test.passes()
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%Error: t/t_langext_2.v:46:7: syntax error, unexpected IDENTIFIER-for-type
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46 | genvar i;
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| ^~~~~~
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: t/t_langext_2.v:49:21: syntax error, unexpected case
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49 | unique0 case (i)
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| ^~~~
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%Error: Cannot continue
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... This fatal error may be caused by the earlier error(s); resolve those first.
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@ -13,6 +13,6 @@ test.scenarios('linter')
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test.top_filename = "t/t_langext_2.v"
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# This is a lint only test.
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test.lint(v_flags2=["+1364-1995ext+v"], fails=True)
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test.lint(v_flags2=["+1364-1995ext+v"], fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,5 @@
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%Error: t/t_langext_3.v:20:4: Can't find typedef/interface: 'uwire'
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20 | uwire w;
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| ^~~~~
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Exiting due to
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@ -13,6 +13,6 @@ test.scenarios('linter')
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test.top_filename = "t/t_langext_3.v"
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# This is a lint only test.
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test.lint(v_flags2=["+1364-2001ext+v"], fails=True)
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test.lint(v_flags2=["+1364-2001ext+v"], fails=True, expect_filename=test.golden_filename)
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test.passes()
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%Error: t/t_langext_2.v:49:21: syntax error, unexpected case
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49 | unique0 case (i)
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| ^~~~
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Cannot continue
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... This fatal error may be caused by the earlier error(s); resolve those first.
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@ -13,6 +13,6 @@ test.scenarios('linter')
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test.top_filename = "t/t_langext_2.v"
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# This is a lint only test.
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test.lint(v_flags2=["+1800-2005ext+v"], fails=True)
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test.lint(v_flags2=["+1800-2005ext+v"], fails=True, expect_filename=test.golden_filename)
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test.passes()
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%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:46:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst'
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: ... note: In instance 't'
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46 | rst <= 1'b0;
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| ^~~
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... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest
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%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:50:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst'
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: ... note: In instance 't'
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50 | rst <= 1'b1;
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| ^~~
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%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:53:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst'
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: ... note: In instance 't'
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53 | rst <= 1'b0;
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| ^~~
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%Error: Exiting due to
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@ -11,6 +11,6 @@ import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=True)
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -14,10 +14,6 @@ module t (/*AUTOARG*/
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wire [1:0] x = { x[0], clk };
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initial begin
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x = 0;
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end
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always @(posedge clk or negedge clk) begin
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`ifdef TEST_VERBOSE
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@ -15,10 +15,6 @@ module t (/*AUTOARG*/
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wire [2:0] x;
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initial begin
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x = 3'b000;
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end
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test1 test1i ( .clk (clk),
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.xvecin (x[1:0]),
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.xvecout (x[2:1]));
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%Warning-UNOPTFLAT: t/t_unoptflat_simple_3.v:16:15: Signal unoptimizable: Circular combinational logic: 't.x'
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16 | wire [2:0] x;
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| ^
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... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
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... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
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t/t_unoptflat_simple_3.v:16:15: Example path: t.x
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t/t_unoptflat_simple_3.v:55:19: Example path: ASSIGNW
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t/t_unoptflat_simple_3.v:53:22: Example path: t.__Vcellout__test1i__xvecout
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t/t_unoptflat_simple_3.v:20:20: Example path: ASSIGNW
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t/t_unoptflat_simple_3.v:16:15: Example path: t.x
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%Error: Exiting due to
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@ -13,6 +13,6 @@ test.scenarios('simulator')
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test.top_filename = "t/t_unoptflat_simple_3.v"
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# Compile only
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test.compile(verilator_flags2=["-fno-dfg"], fails=True)
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test.compile(verilator_flags2=["-fno-dfg"], fails=True, expect_filename=test.golden_filename)
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test.passes()
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%Warning-UNOPTFLAT: t/t_unoptflat_simple.v:15:15: Signal unoptimizable: Circular combinational logic: 't.x'
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15 | wire [1:0] x = { x[0], clk };
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| ^
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... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
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... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
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t/t_unoptflat_simple.v:15:15: Example path: t.x
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t/t_unoptflat_simple.v:15:17: Example path: ASSIGNW
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t/t_unoptflat_simple.v:15:15: Example path: t.x
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%Error: Exiting due to
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@ -13,6 +13,6 @@ test.scenarios('simulator')
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test.top_filename = "t/t_unoptflat_simple.v"
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# Compile only
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test.compile(verilator_flags2=["-fno-dfg"], fails=True)
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test.compile(verilator_flags2=["-fno-dfg"], fails=True, expect_filename=test.golden_filename)
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test.passes()
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