From c73259d2f0ee3f0d16857f21b49a54bc03b9fe55 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 30 Aug 2025 20:35:32 -0400 Subject: [PATCH] Tests: Upgrade some failing tests without expected .out files. --- test_regress/t/t_const_slicesel_bad.out | 6 ++++++ test_regress/t/t_const_slicesel_bad.py | 2 +- test_regress/t/t_dist_warn_coverage.py | 5 ----- test_regress/t/t_flag_language_bad.out | 3 +++ test_regress/t/t_flag_language_bad.py | 4 +++- test_regress/t/t_fuzz_eof_bad.out | 10 ++++++++++ test_regress/t/t_fuzz_eof_bad.py | 2 +- test_regress/t/t_langext_1_bad.out | 9 +++++++++ test_regress/t/t_langext_1_bad.py | 2 +- test_regress/t/t_langext_1d_bad.out | 9 +++++++++ test_regress/t/t_langext_1d_bad.py | 2 +- test_regress/t/t_langext_2_bad.out | 9 +++++++++ test_regress/t/t_langext_2_bad.py | 2 +- test_regress/t/t_langext_3_bad.out | 5 +++++ test_regress/t/t_langext_3_bad.py | 2 +- test_regress/t/t_langext_4_bad.out | 6 ++++++ test_regress/t/t_langext_4_bad.py | 2 +- test_regress/t/t_mem_slice_conc_bad.out | 14 ++++++++++++++ test_regress/t/t_mem_slice_conc_bad.py | 2 +- test_regress/t/t_unoptflat_simple.v | 4 ---- test_regress/t/t_unoptflat_simple_3.v | 4 ---- test_regress/t/t_unoptflat_simple_3_bad.out | 11 +++++++++++ test_regress/t/t_unoptflat_simple_3_bad.py | 2 +- test_regress/t/t_unoptflat_simple_bad.out | 9 +++++++++ test_regress/t/t_unoptflat_simple_bad.py | 2 +- 25 files changed, 104 insertions(+), 24 deletions(-) create mode 100644 test_regress/t/t_const_slicesel_bad.out create mode 100644 test_regress/t/t_flag_language_bad.out create mode 100644 test_regress/t/t_fuzz_eof_bad.out create mode 100644 test_regress/t/t_langext_1_bad.out create mode 100644 test_regress/t/t_langext_1d_bad.out create mode 100644 test_regress/t/t_langext_2_bad.out create mode 100644 test_regress/t/t_langext_3_bad.out create mode 100644 test_regress/t/t_langext_4_bad.out create mode 100644 test_regress/t/t_mem_slice_conc_bad.out create mode 100644 test_regress/t/t_unoptflat_simple_3_bad.out create mode 100644 test_regress/t/t_unoptflat_simple_bad.out diff --git a/test_regress/t/t_const_slicesel_bad.out b/test_regress/t/t_const_slicesel_bad.out new file mode 100644 index 000000000..27d3fb25e --- /dev/null +++ b/test_regress/t/t_const_slicesel_bad.out @@ -0,0 +1,6 @@ +%Error: t/t_const_slicesel_bad.v:12:42: Slice selection index '[3:1]' outside data type's '[2:0]' + : ... note: In instance 't' + 12 | localparam int unsigned B32_T[1:0] = A3[3:1]; + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_const_slicesel_bad.py b/test_regress/t/t_const_slicesel_bad.py index 415956256..726bc29ec 100755 --- a/test_regress/t/t_const_slicesel_bad.py +++ b/test_regress/t/t_const_slicesel_bad.py @@ -12,6 +12,6 @@ import vltest_bootstrap test.scenarios('linter') -test.lint(fails=True) +test.lint(fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_dist_warn_coverage.py b/test_regress/t/t_dist_warn_coverage.py index 5633d45f8..6361676f0 100755 --- a/test_regress/t/t_dist_warn_coverage.py +++ b/test_regress/t/t_dist_warn_coverage.py @@ -28,12 +28,9 @@ for s in [ 'EOF in unterminated string', # Instead get normal unterminated 'Enum ranges must be integral, per spec', # Hard to hit 'Expecting define formal arguments. Found: ', # Instead define syntax error - 'Import package not found: ', # Errors earlier, until future parser released - 'Member selection of non-struct/union object \'', # Instead dotted expression error or V3Link other 'Return with return value isn\'t underneath a function', # Hard to hit, get other bad return messages 'Syntax error parsing real: \'', # Instead can't lex the number 'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance ', # Instead get syntax error - 'Unsupported: Ranges ignored in port-lists', # Hard to hit 'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error # Not yet analyzed '--pipe-filter protocol error, unexpected: ', @@ -53,7 +50,6 @@ for s in [ 'Illegal +: or -: select; type already selected, or bad dimension: ', 'Illegal bit or array select; type already selected, or bad dimension: ', 'Illegal range select; type already selected, or bad dimension: ', - 'Interface port ', 'Interface port declaration ', 'Modport item is not a function/task: ', 'Modport item is not a variable: ', @@ -64,7 +60,6 @@ for s in [ 'Parameter type pin value isn\'t a type: Param ', 'Parameter type variable isn\'t a type: Param ', 'Pattern replication value of 0 is not legal.', - 'Reference to \'', 'Signals inside functions/tasks cannot be marked forceable', 'Slice size cannot be zero.', 'Slices of arrays in assignments have different unpacked dimensions, ', diff --git a/test_regress/t/t_flag_language_bad.out b/test_regress/t/t_flag_language_bad.out new file mode 100644 index 000000000..3e59ce7d8 --- /dev/null +++ b/test_regress/t/t_flag_language_bad.out @@ -0,0 +1,3 @@ +%Error: Unknown language specified: 1-2-3-4 + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_flag_language_bad.py b/test_regress/t/t_flag_language_bad.py index fb255200c..691152651 100755 --- a/test_regress/t/t_flag_language_bad.py +++ b/test_regress/t/t_flag_language_bad.py @@ -11,6 +11,8 @@ import vltest_bootstrap test.scenarios('vlt') -test.lint(verilator_flags2=['--language 1-2-3-4'], fails=True) +test.lint(verilator_flags2=['--language 1-2-3-4'], + fails=True, + expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_fuzz_eof_bad.out b/test_regress/t/t_fuzz_eof_bad.out new file mode 100644 index 000000000..f46de5f58 --- /dev/null +++ b/test_regress/t/t_fuzz_eof_bad.out @@ -0,0 +1,10 @@ +%Error: t/t_fuzz_eof_bad.v:3:31: Unterminated string + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_fuzz_eof_bad.v:2:21: EOF in (* + 2 | initial $lay(*Hello!=nendmodule + | ^ +%Error: t/t_fuzz_eof_bad.v:2:21: syntax error, unexpected end of file + 2 | initial $lay(*Hello!=nendmodule + | ^ +%Error: Cannot continue + ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_fuzz_eof_bad.py b/test_regress/t/t_fuzz_eof_bad.py index d14db8ce3..31228c9a7 100755 --- a/test_regress/t/t_fuzz_eof_bad.py +++ b/test_regress/t/t_fuzz_eof_bad.py @@ -11,6 +11,6 @@ import vltest_bootstrap test.scenarios('linter') -test.lint(fails=True) +test.lint(fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_langext_1_bad.out b/test_regress/t/t_langext_1_bad.out new file mode 100644 index 000000000..c0416843a --- /dev/null +++ b/test_regress/t/t_langext_1_bad.out @@ -0,0 +1,9 @@ +%Error: t/t_langext_1.v:44:7: syntax error, unexpected IDENTIFIER-for-type + 44 | genvar i; + | ^~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_langext_1.v:51:1: syntax error, unexpected endmodule, expecting '(' + 51 | endmodule + | ^~~~~~~~~ +%Error: Cannot continue + ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_langext_1_bad.py b/test_regress/t/t_langext_1_bad.py index f09919252..9e934179f 100755 --- a/test_regress/t/t_langext_1_bad.py +++ b/test_regress/t/t_langext_1_bad.py @@ -13,6 +13,6 @@ test.scenarios('linter') test.top_filename = "t/t_langext_1.v" # This is a lint only test. -test.lint(v_flags2=["+verilog1995ext+v"], fails=True) +test.lint(v_flags2=["+verilog1995ext+v"], fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_langext_1d_bad.out b/test_regress/t/t_langext_1d_bad.out new file mode 100644 index 000000000..c0416843a --- /dev/null +++ b/test_regress/t/t_langext_1d_bad.out @@ -0,0 +1,9 @@ +%Error: t/t_langext_1.v:44:7: syntax error, unexpected IDENTIFIER-for-type + 44 | genvar i; + | ^~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_langext_1.v:51:1: syntax error, unexpected endmodule, expecting '(' + 51 | endmodule + | ^~~~~~~~~ +%Error: Cannot continue + ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_langext_1d_bad.py b/test_regress/t/t_langext_1d_bad.py index 706e9ab40..8709d2908 100755 --- a/test_regress/t/t_langext_1d_bad.py +++ b/test_regress/t/t_langext_1d_bad.py @@ -13,6 +13,6 @@ test.scenarios('linter') test.top_filename = "t/t_langext_1.v" # This is a lint only test. -test.lint(v_flags2=["+verilog1995ext+.v"], fails=True) +test.lint(v_flags2=["+verilog1995ext+.v"], fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_langext_2_bad.out b/test_regress/t/t_langext_2_bad.out new file mode 100644 index 000000000..74b9a1dfa --- /dev/null +++ b/test_regress/t/t_langext_2_bad.out @@ -0,0 +1,9 @@ +%Error: t/t_langext_2.v:46:7: syntax error, unexpected IDENTIFIER-for-type + 46 | genvar i; + | ^~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_langext_2.v:49:21: syntax error, unexpected case + 49 | unique0 case (i) + | ^~~~ +%Error: Cannot continue + ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_langext_2_bad.py b/test_regress/t/t_langext_2_bad.py index 2c8cce718..8e8beacd0 100755 --- a/test_regress/t/t_langext_2_bad.py +++ b/test_regress/t/t_langext_2_bad.py @@ -13,6 +13,6 @@ test.scenarios('linter') test.top_filename = "t/t_langext_2.v" # This is a lint only test. -test.lint(v_flags2=["+1364-1995ext+v"], fails=True) +test.lint(v_flags2=["+1364-1995ext+v"], fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_langext_3_bad.out b/test_regress/t/t_langext_3_bad.out new file mode 100644 index 000000000..c9a25f506 --- /dev/null +++ b/test_regress/t/t_langext_3_bad.out @@ -0,0 +1,5 @@ +%Error: t/t_langext_3.v:20:4: Can't find typedef/interface: 'uwire' + 20 | uwire w; + | ^~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_langext_3_bad.py b/test_regress/t/t_langext_3_bad.py index b0cb8ed8e..179695a06 100755 --- a/test_regress/t/t_langext_3_bad.py +++ b/test_regress/t/t_langext_3_bad.py @@ -13,6 +13,6 @@ test.scenarios('linter') test.top_filename = "t/t_langext_3.v" # This is a lint only test. -test.lint(v_flags2=["+1364-2001ext+v"], fails=True) +test.lint(v_flags2=["+1364-2001ext+v"], fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_langext_4_bad.out b/test_regress/t/t_langext_4_bad.out new file mode 100644 index 000000000..a34467385 --- /dev/null +++ b/test_regress/t/t_langext_4_bad.out @@ -0,0 +1,6 @@ +%Error: t/t_langext_2.v:49:21: syntax error, unexpected case + 49 | unique0 case (i) + | ^~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Cannot continue + ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_langext_4_bad.py b/test_regress/t/t_langext_4_bad.py index fa9e4431d..2a51ace1f 100755 --- a/test_regress/t/t_langext_4_bad.py +++ b/test_regress/t/t_langext_4_bad.py @@ -13,6 +13,6 @@ test.scenarios('linter') test.top_filename = "t/t_langext_2.v" # This is a lint only test. -test.lint(v_flags2=["+1800-2005ext+v"], fails=True) +test.lint(v_flags2=["+1800-2005ext+v"], fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_mem_slice_conc_bad.out b/test_regress/t/t_mem_slice_conc_bad.out new file mode 100644 index 000000000..075f73973 --- /dev/null +++ b/test_regress/t/t_mem_slice_conc_bad.out @@ -0,0 +1,14 @@ +%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:46:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' + : ... note: In instance 't' + 46 | rst <= 1'b0; + | ^~~ + ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest +%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:50:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' + : ... note: In instance 't' + 50 | rst <= 1'b1; + | ^~~ +%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:53:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' + : ... note: In instance 't' + 53 | rst <= 1'b0; + | ^~~ +%Error: Exiting due to diff --git a/test_regress/t/t_mem_slice_conc_bad.py b/test_regress/t/t_mem_slice_conc_bad.py index d14db8ce3..31228c9a7 100755 --- a/test_regress/t/t_mem_slice_conc_bad.py +++ b/test_regress/t/t_mem_slice_conc_bad.py @@ -11,6 +11,6 @@ import vltest_bootstrap test.scenarios('linter') -test.lint(fails=True) +test.lint(fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_unoptflat_simple.v b/test_regress/t/t_unoptflat_simple.v index 76ca19e95..2198ae1b8 100644 --- a/test_regress/t/t_unoptflat_simple.v +++ b/test_regress/t/t_unoptflat_simple.v @@ -14,10 +14,6 @@ module t (/*AUTOARG*/ wire [1:0] x = { x[0], clk }; - initial begin - x = 0; - end - always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE diff --git a/test_regress/t/t_unoptflat_simple_3.v b/test_regress/t/t_unoptflat_simple_3.v index 8e1ed888e..f275a2e02 100644 --- a/test_regress/t/t_unoptflat_simple_3.v +++ b/test_regress/t/t_unoptflat_simple_3.v @@ -15,10 +15,6 @@ module t (/*AUTOARG*/ wire [2:0] x; - initial begin - x = 3'b000; - end - test1 test1i ( .clk (clk), .xvecin (x[1:0]), .xvecout (x[2:1])); diff --git a/test_regress/t/t_unoptflat_simple_3_bad.out b/test_regress/t/t_unoptflat_simple_3_bad.out new file mode 100644 index 000000000..58aac8860 --- /dev/null +++ b/test_regress/t/t_unoptflat_simple_3_bad.out @@ -0,0 +1,11 @@ +%Warning-UNOPTFLAT: t/t_unoptflat_simple_3.v:16:15: Signal unoptimizable: Circular combinational logic: 't.x' + 16 | wire [2:0] x; + | ^ + ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest + ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. + t/t_unoptflat_simple_3.v:16:15: Example path: t.x + t/t_unoptflat_simple_3.v:55:19: Example path: ASSIGNW + t/t_unoptflat_simple_3.v:53:22: Example path: t.__Vcellout__test1i__xvecout + t/t_unoptflat_simple_3.v:20:20: Example path: ASSIGNW + t/t_unoptflat_simple_3.v:16:15: Example path: t.x +%Error: Exiting due to diff --git a/test_regress/t/t_unoptflat_simple_3_bad.py b/test_regress/t/t_unoptflat_simple_3_bad.py index 02fe09491..3f1eae376 100755 --- a/test_regress/t/t_unoptflat_simple_3_bad.py +++ b/test_regress/t/t_unoptflat_simple_3_bad.py @@ -13,6 +13,6 @@ test.scenarios('simulator') test.top_filename = "t/t_unoptflat_simple_3.v" # Compile only -test.compile(verilator_flags2=["-fno-dfg"], fails=True) +test.compile(verilator_flags2=["-fno-dfg"], fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_unoptflat_simple_bad.out b/test_regress/t/t_unoptflat_simple_bad.out new file mode 100644 index 000000000..e0a88d651 --- /dev/null +++ b/test_regress/t/t_unoptflat_simple_bad.out @@ -0,0 +1,9 @@ +%Warning-UNOPTFLAT: t/t_unoptflat_simple.v:15:15: Signal unoptimizable: Circular combinational logic: 't.x' + 15 | wire [1:0] x = { x[0], clk }; + | ^ + ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest + ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. + t/t_unoptflat_simple.v:15:15: Example path: t.x + t/t_unoptflat_simple.v:15:17: Example path: ASSIGNW + t/t_unoptflat_simple.v:15:15: Example path: t.x +%Error: Exiting due to diff --git a/test_regress/t/t_unoptflat_simple_bad.py b/test_regress/t/t_unoptflat_simple_bad.py index 6440259f5..45a8f5331 100755 --- a/test_regress/t/t_unoptflat_simple_bad.py +++ b/test_regress/t/t_unoptflat_simple_bad.py @@ -13,6 +13,6 @@ test.scenarios('simulator') test.top_filename = "t/t_unoptflat_simple.v" # Compile only -test.compile(verilator_flags2=["-fno-dfg"], fails=True) +test.compile(verilator_flags2=["-fno-dfg"], fails=True, expect_filename=test.golden_filename) test.passes()