Fix FSM coverage hierarchy being emitted as an absolute path (#8421)

AstNodeCoverDecl::hier() is relative to the scope the declaration is
emitted from, as V3EmitCImp builds the reported path as 'vlNamep + hierp',
and that is how V3Coverage uses it. V3FsmDetect instead set it to the
absolute scope name, so the instance path was counted twice.

This was masked whenever the owning module was inlined, as the declaration
then ended up in the top scope. With inlining disabled, an FSM in an
instance reported 'top.t.forced_wide_u.t.forced_wide_u'. In the inlined
case it reported 'top.TOP', leaking the internal top wrapper name into
user visible coverage output, rather than plain 'top'.

src/V3FsmDetect.cpp

@@ -2194,7 +2194,6 @@ class FsmLowerVisitor final {
                                         graph.stateVarName(),
                                         "",
                                         statep->label()};
-            declp->hier(scopep->prettyName());
             modp->addStmtsp(declp);
             AstNodeExpr* const guardp
                 = andExpr(flp,
@@ -2231,7 +2230,6 @@ class FsmLowerVisitor final {
                                             fromVertexp->label(),
                                             toStatep->label(),
                                             fsmTag};
-                declp->hier(scopep->prettyName());
                 modp->addStmtsp(declp);
                 AstNodeExpr* guardp = nullptr;
                 if (fromVertexp->isResetAny()) {

test_regress/t/t_cover_fsm_plain_always_zerohit_multi.out

@@ -1,9 +1,9 @@
 # SystemC::Coverage-3
-C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l28
n5
tfsm_arc
pagev_fsm_arc/$root
ot.near_canonical_state_d_case_u.state_d::S0->S1
Fvt.near_canonical_state_d_case_u.state_d
FfS0
FtS1
htop.TOP' 0
-C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l28
n5
tfsm_arc
pagev_fsm_arc/$root
ot.near_canonical_state_d_case_u.state_d::S0->S2
Fvt.near_canonical_state_d_case_u.state_d
FfS0
FtS2
htop.TOP' 0
-C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l28
n5
tfsm_state
pagev_fsm_state/$root
ot.near_canonical_state_d_case_u.state_d::S0
Fvt.near_canonical_state_d_case_u.state_d
FtS0
htop.TOP' 0
-C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l28
n5
tfsm_state
pagev_fsm_state/$root
ot.near_canonical_state_d_case_u.state_d::S1
Fvt.near_canonical_state_d_case_u.state_d
FtS1
htop.TOP' 0
-C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l28
n5
tfsm_state
pagev_fsm_state/$root
ot.near_canonical_state_d_case_u.state_d::S2
Fvt.near_canonical_state_d_case_u.state_d
FtS2
htop.TOP' 0
-C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l60
n5
tfsm_state
pagev_fsm_state/$root
ot.selector_matches_noassign_u.state_q::S0
Fvt.selector_matches_noassign_u.state_q
FtS0
htop.TOP' 0
-C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l60
n5
tfsm_state
pagev_fsm_state/$root
ot.selector_matches_noassign_u.state_q::S1
Fvt.selector_matches_noassign_u.state_q
FtS1
htop.TOP' 0
-C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l60
n5
tfsm_state
pagev_fsm_state/$root
ot.selector_matches_noassign_u.state_q::S2
Fvt.selector_matches_noassign_u.state_q
FtS2
htop.TOP' 0
+C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l28
n5
tfsm_arc
pagev_fsm_arc/$root
ot.near_canonical_state_d_case_u.state_d::S0->S1
Fvt.near_canonical_state_d_case_u.state_d
FfS0
FtS1
htop' 0
+C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l28
n5
tfsm_arc
pagev_fsm_arc/$root
ot.near_canonical_state_d_case_u.state_d::S0->S2
Fvt.near_canonical_state_d_case_u.state_d
FfS0
FtS2
htop' 0
+C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l28
n5
tfsm_state
pagev_fsm_state/$root
ot.near_canonical_state_d_case_u.state_d::S0
Fvt.near_canonical_state_d_case_u.state_d
FtS0
htop' 0
+C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l28
n5
tfsm_state
pagev_fsm_state/$root
ot.near_canonical_state_d_case_u.state_d::S1
Fvt.near_canonical_state_d_case_u.state_d
FtS1
htop' 0
+C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l28
n5
tfsm_state
pagev_fsm_state/$root
ot.near_canonical_state_d_case_u.state_d::S2
Fvt.near_canonical_state_d_case_u.state_d
FtS2
htop' 0
+C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l60
n5
tfsm_state
pagev_fsm_state/$root
ot.selector_matches_noassign_u.state_q::S0
Fvt.selector_matches_noassign_u.state_q
FtS0
htop' 0
+C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l60
n5
tfsm_state
pagev_fsm_state/$root
ot.selector_matches_noassign_u.state_q::S1
Fvt.selector_matches_noassign_u.state_q
FtS1
htop' 0
+C '
ft/t_cover_fsm_plain_always_zerohit_multi.v
l60
n5
tfsm_state
pagev_fsm_state/$root
ot.selector_matches_noassign_u.state_q::S2
Fvt.selector_matches_noassign_u.state_q
FtS2
htop' 0

test_regress/t/t_cover_fsm_transition_shapes_multi.out

@@ -1,11 +1,11 @@
 # SystemC::Coverage-3
-C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_arc
pagev_fsm_arc/$root
ot.forced_wide_u.state::31'h0->31'h1
Fvt.forced_wide_u.state
Ff31'h0
Ft31'h1
htop.TOP' 2
-C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_arc
pagev_fsm_arc/$root
ot.forced_wide_u.state::31'h1->31'h2
Fvt.forced_wide_u.state
Ff31'h1
Ft31'h2
htop.TOP' 2
-C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_arc
pagev_fsm_arc/$root
ot.forced_wide_u.state::ANY->31'h0[reset]
Fvt.forced_wide_u.state
FfANY
Ft31'h0
Fgreset
htop.TOP' 1
-C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_state
pagev_fsm_state/$root
ot.forced_wide_u.state::31'h0
Fvt.forced_wide_u.state
Ft31'h0
htop.TOP' 1
-C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_state
pagev_fsm_state/$root
ot.forced_wide_u.state::31'h1
Fvt.forced_wide_u.state
Ft31'h1
htop.TOP' 2
-C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_state
pagev_fsm_state/$root
ot.forced_wide_u.state::31'h2
Fvt.forced_wide_u.state
Ft31'h2
htop.TOP' 2
-C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_arc
pagev_fsm_arc/$root
ot.forced_if_wide_u.state::31'h0->31'h1
Fvt.forced_if_wide_u.state
Ff31'h0
Ft31'h1
htop.TOP' 4
-C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_arc
pagev_fsm_arc/$root
ot.forced_if_wide_u.state::31'h1->31'h0
Fvt.forced_if_wide_u.state
Ff31'h1
Ft31'h0
htop.TOP' 3
-C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_state
pagev_fsm_state/$root
ot.forced_if_wide_u.state::31'h0
Fvt.forced_if_wide_u.state
Ft31'h0
htop.TOP' 3
-C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_state
pagev_fsm_state/$root
ot.forced_if_wide_u.state::31'h1
Fvt.forced_if_wide_u.state
Ft31'h1
htop.TOP' 4
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_arc
pagev_fsm_arc/$root
ot.forced_wide_u.state::31'h0->31'h1
Fvt.forced_wide_u.state
Ff31'h0
Ft31'h1
htop' 2
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_arc
pagev_fsm_arc/$root
ot.forced_wide_u.state::31'h1->31'h2
Fvt.forced_wide_u.state
Ff31'h1
Ft31'h2
htop' 2
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_arc
pagev_fsm_arc/$root
ot.forced_wide_u.state::ANY->31'h0[reset]
Fvt.forced_wide_u.state
FfANY
Ft31'h0
Fgreset
htop' 1
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_state
pagev_fsm_state/$root
ot.forced_wide_u.state::31'h0
Fvt.forced_wide_u.state
Ft31'h0
htop' 1
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_state
pagev_fsm_state/$root
ot.forced_wide_u.state::31'h1
Fvt.forced_wide_u.state
Ft31'h1
htop' 2
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_state
pagev_fsm_state/$root
ot.forced_wide_u.state::31'h2
Fvt.forced_wide_u.state
Ft31'h2
htop' 2
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_arc
pagev_fsm_arc/$root
ot.forced_if_wide_u.state::31'h0->31'h1
Fvt.forced_if_wide_u.state
Ff31'h0
Ft31'h1
htop' 4
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_arc
pagev_fsm_arc/$root
ot.forced_if_wide_u.state::31'h1->31'h0
Fvt.forced_if_wide_u.state
Ff31'h1
Ft31'h0
htop' 3
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_state
pagev_fsm_state/$root
ot.forced_if_wide_u.state::31'h0
Fvt.forced_if_wide_u.state
Ft31'h0
htop' 3
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_state
pagev_fsm_state/$root
ot.forced_if_wide_u.state::31'h1
Fvt.forced_if_wide_u.state
Ft31'h1
htop' 4

test_regress/t/t_cover_fsm_transition_shapes_no_inline.out

@@ -0,0 +1,11 @@
+# SystemC::Coverage-3
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_arc
pagev_fsm_arc/fsm_forced_wide
ot.forced_wide_u.state::31'h0->31'h1
Fvt.forced_wide_u.state
Ff31'h0
Ft31'h1
htop.t.forced_wide_u' 2
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_arc
pagev_fsm_arc/fsm_forced_wide
ot.forced_wide_u.state::31'h1->31'h2
Fvt.forced_wide_u.state
Ff31'h1
Ft31'h2
htop.t.forced_wide_u' 2
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_arc
pagev_fsm_arc/fsm_forced_wide
ot.forced_wide_u.state::ANY->31'h0[reset]
Fvt.forced_wide_u.state
FfANY
Ft31'h0
Fgreset
htop.t.forced_wide_u' 1
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_state
pagev_fsm_state/fsm_forced_wide
ot.forced_wide_u.state::31'h0
Fvt.forced_wide_u.state
Ft31'h0
htop.t.forced_wide_u' 1
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_state
pagev_fsm_state/fsm_forced_wide
ot.forced_wide_u.state::31'h1
Fvt.forced_wide_u.state
Ft31'h1
htop.t.forced_wide_u' 2
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l724
n7
tfsm_state
pagev_fsm_state/fsm_forced_wide
ot.forced_wide_u.state::31'h2
Fvt.forced_wide_u.state
Ft31'h2
htop.t.forced_wide_u' 2
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_arc
pagev_fsm_arc/fsm_forced_if_wide
ot.forced_if_wide_u.state::31'h0->31'h1
Fvt.forced_if_wide_u.state
Ff31'h0
Ft31'h1
htop.t.forced_if_wide_u' 4
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_arc
pagev_fsm_arc/fsm_forced_if_wide
ot.forced_if_wide_u.state::31'h1->31'h0
Fvt.forced_if_wide_u.state
Ff31'h1
Ft31'h0
htop.t.forced_if_wide_u' 3
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_state
pagev_fsm_state/fsm_forced_if_wide
ot.forced_if_wide_u.state::31'h0
Fvt.forced_if_wide_u.state
Ft31'h0
htop.t.forced_if_wide_u' 3
+C '
ft/t_cover_fsm_transition_shapes_multi.v
l742
n5
tfsm_state
pagev_fsm_state/fsm_forced_if_wide
ot.forced_if_wide_u.state::31'h1
Fvt.forced_if_wide_u.state
Ft31'h1
htop.t.forced_if_wide_u' 4

test_regress/t/t_cover_fsm_transition_shapes_no_inline.py

@@ -0,0 +1,32 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: FSM coverage hierarchy with module inlining disabled
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+# Same as t_cover_fsm_transition_shapes_multi, but without module inlining, so
+# the coverage declarations stay in the scope of the instance that owns them.
+# The emitted hierarchy is the scope name plus AstNodeCoverDecl::hier(), so hier
+# must be relative to that scope.
+#
+# Note this golden still differs from the inlined one, which reports the top
+# scope and '$root', because V3FsmDetect::detect runs after V3Inline and so only
+# ever sees the flattened design. Were it to run before, V3Inline would prefix
+# the instance names onto hier and both would report the same, at which point
+# this test should compare against t_cover_fsm_transition_shapes_multi.out.
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_cover_fsm_transition_shapes_multi.v"
+
+test.compile(verilator_flags2=['--cc --coverage-fsm', '-fno-inline'])
+
+test.execute()
+
+test.files_identical(test.obj_dir + "/coverage.dat", "t/" + test.name + ".out")
+
+test.passes()