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Fix URL references.

This commit is contained in:
Wilson Snyder 2021-04-18 11:52:29 -04:00
parent 2e9e4ae110
commit c443e229ee
14 changed files with 20 additions and 18 deletions
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2
docs/internals.rst
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@ -707,7 +707,7 @@ Testing
======= =======
For an overview of how to write a test see the BUGS section of the For an overview of how to write a test see the BUGS section of the
Verilator primary manual. `Verilator Manual <https://verilator.org/verilator_doc.html>`_.
It is important to add tests for failures as well as success (for It is important to add tests for failures as well as success (for
example to check that an error message is correctly triggered). example to check that an error message is correctly triggered).

3
src/V3EmitC.cpp
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@ -1097,6 +1097,7 @@ public:
iterateAndNextNull(nodep->fhsp()); iterateAndNextNull(nodep->fhsp());
puts(")"); puts(")");
} }
virtual void visit(AstInitItem* nodep) override { iterateChildren(nodep); }
// Terminals // Terminals
virtual void visit(AstVarRef* nodep) override { virtual void visit(AstVarRef* nodep) override {
puts(nodep->hiernameProtect()); puts(nodep->hiernameProtect());
@ -2734,7 +2735,7 @@ void EmitCImp::emitSettleLoop(const std::string& eval_call, bool initial) {
puts("\"Verilated model didn't "); puts("\"Verilated model didn't ");
if (initial) puts("DC "); if (initial) puts("DC ");
puts("converge\\n\"\n"); puts("converge\\n\"\n");
puts("\"- See DIDNOTCONVERGE in the Verilator manual\");\n"); puts("\"- See https://verilator.org/warn/DIDNOTCONVERGE\");\n");
puts("} else {\n"); puts("} else {\n");
puts("__Vchange = " + protect("_change_request") + "(vlSymsp);\n"); puts("__Vchange = " + protect("_change_request") + "(vlSymsp);\n");
puts("}\n"); puts("}\n");

9
src/V3Error.cpp
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@ -242,7 +242,8 @@ void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) {
<< " */\" and lint_on around source to disable this message." << endl; << " */\" and lint_on around source to disable this message." << endl;
} }
if (s_errorCode.dangerous()) { if (s_errorCode.dangerous()) {
std::cerr << warnMore() << "*** See the manual before disabling this,\n"; std::cerr << warnMore() << "*** See https://verilator.org/warn/"
<< s_errorCode.ascii() << " before disabling this,\n";
std::cerr << warnMore() << "else you may end up with different sim results." std::cerr << warnMore() << "else you may end up with different sim results."
<< endl; << endl;
} }
@ -267,9 +268,9 @@ void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) {
if (!inFatal) { if (!inFatal) {
inFatal = true; inFatal = true;
if (s_tellManual == 1) { if (s_tellManual == 1) {
std::cerr std::cerr << warnMore()
<< warnMore() << "... See the manual at https://verilator.org/verilator_doc.html "
<< "... See the manual and https://verilator.org for more assistance." "for more assistance."
<< endl; << endl;
s_tellManual = 2; s_tellManual = 2;
} }

2
test_regress/t/t_debug_fatalsrc_bad.pl
View File

@ -15,7 +15,7 @@ lint(
fails => $Self->{vlt_all}, fails => $Self->{vlt_all},
expect => expect =>
'%Error: Internal Error: .*: --debug-fatal-src '%Error: Internal Error: .*: --debug-fatal-src
.* See the manual and .*', .* See the manual .*',
); );
ok(1); ok(1);

2
test_regress/t/t_debug_fatalsrc_bt_bad.pl
View File

@ -16,7 +16,7 @@ lint(
fails => 1, fails => 1,
expect => expect =>
'%Error: Internal Error: .*: --debug-fatal-src '%Error: Internal Error: .*: --debug-fatal-src
.*See the manual and .* .*See the manual .*
.*in V3Options::.* .*in V3Options::.*
.*%Error: Command Failed.*', .*%Error: Command Failed.*',
); );

2
test_regress/t/t_dpi_accessors.v
View File

@ -9,7 +9,7 @@
// This test exercises the use of DPI to access signals and registers in a // This test exercises the use of DPI to access signals and registers in a
// module hierarchy in a uniform fashion. See the discussion at // module hierarchy in a uniform fashion. See the discussion at
// //
// https://www.veripool.org/boards/3/topics/show/752-Verilator-Command-line-specification-of-public-access-to-variables // https://github.com/verilator/verilator/issues/1750
// //
// We need to test read and write access to: // We need to test read and write access to:
// - scalars // - scalars

2
test_regress/t/t_enum_type_methods_bad.out
View File

@ -2,4 +2,4 @@
: ... In instance t : ... In instance t
24 | e.next(increment); 24 | e.next(increment);
| ^~~~~~~~~ | ^~~~~~~~~
... See the manual and https://verilator.org for more assistance. ... See the manual at https://verilator.org/verilator_doc.html for more assistance.

2
test_regress/t/t_func_tasknsvar_bad.out
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@ -5,4 +5,4 @@
%Error: Internal Error: t/t_func_tasknsvar_bad.v:10:7: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): m_varScopep && !m_varScopep->brokeExists() %Error: Internal Error: t/t_func_tasknsvar_bad.v:10:7: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): m_varScopep && !m_varScopep->brokeExists()
10 | sig = '1; 10 | sig = '1;
| ^~~ | ^~~
... See the manual and https://verilator.org for more assistance. ... See the manual at https://verilator.org/verilator_doc.html for more assistance.

2
test_regress/t/t_fuzz_genintf_bad.out
View File

@ -7,4 +7,4 @@
: ... In instance t : ... In instance t
24 | j.e(0), 24 | j.e(0),
| ^ | ^
... See the manual and https://verilator.org for more assistance. ... See the manual at https://verilator.org/verilator_doc.html for more assistance.

2
test_regress/t/t_fuzz_triand_bad.out
View File

@ -7,4 +7,4 @@
: ... In instance t : ... In instance t
8 | tri g=g.and.g; 8 | tri g=g.and.g;
| ^~~ | ^~~
... See the manual and https://verilator.org for more assistance. ... See the manual at https://verilator.org/verilator_doc.html for more assistance.

2
test_regress/t/t_interface_ar3.out
View File

@ -6,4 +6,4 @@
: ... In instance t : ... In instance t
16 | sub sub01 [2] (.clk, .infc(iinst[0:1])); 16 | sub sub01 [2] (.clk, .infc(iinst[0:1]));
| ^ | ^
... See the manual and https://verilator.org for more assistance. ... See the manual at https://verilator.org/verilator_doc.html for more assistance.

2
test_regress/t/t_lint_blksync_bad.out
View File

@ -8,6 +8,6 @@
: ... Suggest blocking assignments (=) : ... Suggest blocking assignments (=)
31 | combo_nblk <= 1'b1; 31 | combo_nblk <= 1'b1;
| ^~ | ^~
*** See the manual before disabling this, *** See https://verilator.org/warn/COMBDLY before disabling this,
else you may end up with different sim results. else you may end up with different sim results.
%Error: Exiting due to %Error: Exiting due to

2
test_regress/t/t_lint_latch_bad.out
View File

@ -7,6 +7,6 @@
: ... Suggest blocking assignments (=) : ... Suggest blocking assignments (=)
25 | bc <= a; 25 | bc <= a;
| ^~ | ^~
*** See the manual before disabling this, *** See https://verilator.org/warn/COMBDLY before disabling this,
else you may end up with different sim results. else you may end up with different sim results.
%Error: Exiting due to %Error: Exiting due to

2
test_regress/t/t_lint_latch_bad_3.out
View File

@ -8,6 +8,6 @@
: ... Suggest blocking assignments (=) : ... Suggest blocking assignments (=)
70 | o4 <= 1'b0; 70 | o4 <= 1'b0;
| ^~ | ^~
*** See the manual before disabling this, *** See https://verilator.org/warn/COMBDLY before disabling this,
else you may end up with different sim results. else you may end up with different sim results.
%Error: Exiting due to %Error: Exiting due to