diff --git a/docs/internals.rst b/docs/internals.rst index f40cce27b..71eebfb41 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -707,7 +707,7 @@ Testing ======= For an overview of how to write a test see the BUGS section of the -Verilator primary manual. +`Verilator Manual `_. It is important to add tests for failures as well as success (for example to check that an error message is correctly triggered). diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index 48ad6de4a..0785b4f75 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -1097,6 +1097,7 @@ public: iterateAndNextNull(nodep->fhsp()); puts(")"); } + virtual void visit(AstInitItem* nodep) override { iterateChildren(nodep); } // Terminals virtual void visit(AstVarRef* nodep) override { puts(nodep->hiernameProtect()); @@ -2734,7 +2735,7 @@ void EmitCImp::emitSettleLoop(const std::string& eval_call, bool initial) { puts("\"Verilated model didn't "); if (initial) puts("DC "); puts("converge\\n\"\n"); - puts("\"- See DIDNOTCONVERGE in the Verilator manual\");\n"); + puts("\"- See https://verilator.org/warn/DIDNOTCONVERGE\");\n"); puts("} else {\n"); puts("__Vchange = " + protect("_change_request") + "(vlSymsp);\n"); puts("}\n"); diff --git a/src/V3Error.cpp b/src/V3Error.cpp index 23921b0ee..d1f4b4a4f 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -242,7 +242,8 @@ void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) { << " */\" and lint_on around source to disable this message." << endl; } if (s_errorCode.dangerous()) { - std::cerr << warnMore() << "*** See the manual before disabling this,\n"; + std::cerr << warnMore() << "*** See https://verilator.org/warn/" + << s_errorCode.ascii() << " before disabling this,\n"; std::cerr << warnMore() << "else you may end up with different sim results." << endl; } @@ -267,10 +268,10 @@ void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) { if (!inFatal) { inFatal = true; if (s_tellManual == 1) { - std::cerr - << warnMore() - << "... See the manual and https://verilator.org for more assistance." - << endl; + std::cerr << warnMore() + << "... See the manual at https://verilator.org/verilator_doc.html " + "for more assistance." + << endl; s_tellManual = 2; } #ifndef V3ERROR_NO_GLOBAL_ diff --git a/test_regress/t/t_debug_fatalsrc_bad.pl b/test_regress/t/t_debug_fatalsrc_bad.pl index 6f50286a8..c11da33d9 100755 --- a/test_regress/t/t_debug_fatalsrc_bad.pl +++ b/test_regress/t/t_debug_fatalsrc_bad.pl @@ -15,7 +15,7 @@ lint( fails => $Self->{vlt_all}, expect => '%Error: Internal Error: .*: --debug-fatal-src -.* See the manual and .*', +.* See the manual .*', ); ok(1); diff --git a/test_regress/t/t_debug_fatalsrc_bt_bad.pl b/test_regress/t/t_debug_fatalsrc_bt_bad.pl index ad5a9ae03..8be054a7b 100755 --- a/test_regress/t/t_debug_fatalsrc_bt_bad.pl +++ b/test_regress/t/t_debug_fatalsrc_bt_bad.pl @@ -16,7 +16,7 @@ lint( fails => 1, expect => '%Error: Internal Error: .*: --debug-fatal-src -.*See the manual and .* +.*See the manual .* .*in V3Options::.* .*%Error: Command Failed.*', ); diff --git a/test_regress/t/t_dpi_accessors.v b/test_regress/t/t_dpi_accessors.v index 9fe29f04f..c41fea0bc 100644 --- a/test_regress/t/t_dpi_accessors.v +++ b/test_regress/t/t_dpi_accessors.v @@ -9,7 +9,7 @@ // This test exercises the use of DPI to access signals and registers in a // module hierarchy in a uniform fashion. See the discussion at // -// https://www.veripool.org/boards/3/topics/show/752-Verilator-Command-line-specification-of-public-access-to-variables +// https://github.com/verilator/verilator/issues/1750 // // We need to test read and write access to: // - scalars diff --git a/test_regress/t/t_enum_type_methods_bad.out b/test_regress/t/t_enum_type_methods_bad.out index 7bcf19162..41c5834a1 100644 --- a/test_regress/t/t_enum_type_methods_bad.out +++ b/test_regress/t/t_enum_type_methods_bad.out @@ -2,4 +2,4 @@ : ... In instance t 24 | e.next(increment); | ^~~~~~~~~ - ... See the manual and https://verilator.org for more assistance. + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_func_tasknsvar_bad.out b/test_regress/t/t_func_tasknsvar_bad.out index ffcd633c9..b60d15c95 100644 --- a/test_regress/t/t_func_tasknsvar_bad.out +++ b/test_regress/t/t_func_tasknsvar_bad.out @@ -5,4 +5,4 @@ %Error: Internal Error: t/t_func_tasknsvar_bad.v:10:7: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): m_varScopep && !m_varScopep->brokeExists() 10 | sig = '1; | ^~~ - ... See the manual and https://verilator.org for more assistance. + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_fuzz_genintf_bad.out b/test_regress/t/t_fuzz_genintf_bad.out index 485e7289b..df5d490ef 100644 --- a/test_regress/t/t_fuzz_genintf_bad.out +++ b/test_regress/t/t_fuzz_genintf_bad.out @@ -7,4 +7,4 @@ : ... In instance t 24 | j.e(0), | ^ - ... See the manual and https://verilator.org for more assistance. + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_fuzz_triand_bad.out b/test_regress/t/t_fuzz_triand_bad.out index 3343c190b..3af71a1ba 100644 --- a/test_regress/t/t_fuzz_triand_bad.out +++ b/test_regress/t/t_fuzz_triand_bad.out @@ -7,4 +7,4 @@ : ... In instance t 8 | tri g=g.and.g; | ^~~ - ... See the manual and https://verilator.org for more assistance. + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_interface_ar3.out b/test_regress/t/t_interface_ar3.out index e28530a56..49bc89443 100644 --- a/test_regress/t/t_interface_ar3.out +++ b/test_regress/t/t_interface_ar3.out @@ -6,4 +6,4 @@ : ... In instance t 16 | sub sub01 [2] (.clk, .infc(iinst[0:1])); | ^ - ... See the manual and https://verilator.org for more assistance. + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_lint_blksync_bad.out b/test_regress/t/t_lint_blksync_bad.out index ec1d772e9..4e09d0d77 100644 --- a/test_regress/t/t_lint_blksync_bad.out +++ b/test_regress/t/t_lint_blksync_bad.out @@ -8,6 +8,6 @@ : ... Suggest blocking assignments (=) 31 | combo_nblk <= 1'b1; | ^~ - *** See the manual before disabling this, + *** See https://verilator.org/warn/COMBDLY before disabling this, else you may end up with different sim results. %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad.out b/test_regress/t/t_lint_latch_bad.out index 2cd7ce388..1d5cd253a 100644 --- a/test_regress/t/t_lint_latch_bad.out +++ b/test_regress/t/t_lint_latch_bad.out @@ -7,6 +7,6 @@ : ... Suggest blocking assignments (=) 25 | bc <= a; | ^~ - *** See the manual before disabling this, + *** See https://verilator.org/warn/COMBDLY before disabling this, else you may end up with different sim results. %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad_3.out b/test_regress/t/t_lint_latch_bad_3.out index 809fea09a..94f96de5e 100644 --- a/test_regress/t/t_lint_latch_bad_3.out +++ b/test_regress/t/t_lint_latch_bad_3.out @@ -8,6 +8,6 @@ : ... Suggest blocking assignments (=) 70 | o4 <= 1'b0; | ^~ - *** See the manual before disabling this, + *** See https://verilator.org/warn/COMBDLY before disabling this, else you may end up with different sim results. %Error: Exiting due to