parent
331cac2054
commit
c3fc0d9f0f
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@ -467,10 +467,8 @@ class TraceVisitor final : public VNVisitor {
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} else if (AstCFunc* const funcp = VN_CAST(insertp, CFunc)) {
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} else if (AstCFunc* const funcp = VN_CAST(insertp, CFunc)) {
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// If there are awaits, insert the setter after each await
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// If there are awaits, insert the setter after each await
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if (funcp->isCoroutine() && funcp->stmtsp()) {
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if (funcp->isCoroutine() && funcp->stmtsp()) {
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funcp->stmtsp()->foreachAndNext([&](AstCAwait* awaitp) {
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funcp->stmtsp()->foreachAndNext([setterp](AstCAwait* awaitp) {
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AstNode* stmtp = awaitp->backp();
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awaitp->addNextHere(setterp->cloneTree(false));
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while (VN_IS(stmtp, NodeExpr)) stmtp = stmtp->backp();
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stmtp->addNextHere(setterp->cloneTree(false));
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});
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});
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}
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}
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funcp->addStmtsp(setterp);
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funcp->addStmtsp(setterp);
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@ -0,0 +1,35 @@
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$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module t $end
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$var wire 129 " x [128:0] $end
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$upscope $end
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$enddefinitions $end
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#1
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b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "
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#6
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b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
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#10
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b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
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#20
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b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
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#30
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b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
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#40
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b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
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#50
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b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
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#60
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b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
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#70
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b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
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#80
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b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
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#90
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b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
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#100
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b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
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#110
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b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
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#111
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@ -0,0 +1,20 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--binary', '--trace-vcd'])
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test.execute()
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test.vcd_identical(test.trace_filename, test.golden_filename)
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test.passes()
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@ -0,0 +1,25 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t;
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logic [128:0] x = 0;
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always #10 x = ~x;
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initial begin
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#1;
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$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
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$dumpvars();
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#5;
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x = 442093479423423857275364882039482723489;
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#5;
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#100;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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