luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix internal error on wide -x-initial unique (#3106).

This commit is contained in:
Wilson Snyder 2021-08-23 20:13:09 -04:00
parent f9806595f2
commit c3d64d9743
3 changed files with 9 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Changes
View File

@ -27,6 +27,7 @@ Verilator 4.211 devel
* Fix -G to treat simple integer literals as signed (#3060). [Anikin1610] * Fix -G to treat simple integer literals as signed (#3060). [Anikin1610]
* Fix emitted string array initializers (#2895). [Iztok Jeras] * Fix emitted string array initializers (#2895). [Iztok Jeras]
* Fix bitop tree optimization dropping necessary & operator (#3096). [Flavien Solt] * Fix bitop tree optimization dropping necessary & operator (#3096). [Flavien Solt]
* Fix internal error on wide -x-initial unique (#3106). [Alexandre Joannou]
Verilator 4.210 2021-07-07 Verilator 4.210 2021-07-07

4
src/V3Premit.cpp
View File

@ -324,6 +324,10 @@ private:
iterateChildren(nodep); iterateChildren(nodep);
checkNode(nodep); checkNode(nodep);
} }
virtual void visit(AstRand* nodep) override {
iterateChildren(nodep);
checkNode(nodep);
}
virtual void visit(AstUCFunc* nodep) override { virtual void visit(AstUCFunc* nodep) override {
iterateChildren(nodep); iterateChildren(nodep);
checkNode(nodep); checkNode(nodep);

5
test_regress/t/t_flag_xinitial_unique.v
View File

@ -6,10 +6,13 @@
module t (/*AUTOARG*/ module t (/*AUTOARG*/
// Outputs // Outputs
value value, value2
); );
output reg [63:0] value; output reg [63:0] value;
output wire [64:0] value2;
assign value2 = {8'bx, 57'h12};
initial begin initial begin
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");