diff --git a/Changes b/Changes
index e7ddcc712..f3f250292 100644
--- a/Changes
+++ b/Changes
@@ -27,6 +27,7 @@ Verilator 4.211 devel
 * Fix -G to treat simple integer literals as signed (#3060). [Anikin1610]
 * Fix emitted string array initializers (#2895). [Iztok Jeras]
 * Fix bitop tree optimization dropping necessary & operator (#3096). [Flavien Solt]
+* Fix internal error on wide -x-initial unique (#3106). [Alexandre Joannou]
 
 
 Verilator 4.210 2021-07-07
diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp
index e665628b2..1c680382d 100644
--- a/src/V3Premit.cpp
+++ b/src/V3Premit.cpp
@@ -324,6 +324,10 @@ private:
         iterateChildren(nodep);
         checkNode(nodep);
     }
+    virtual void visit(AstRand* nodep) override {
+        iterateChildren(nodep);
+        checkNode(nodep);
+    }
     virtual void visit(AstUCFunc* nodep) override {
         iterateChildren(nodep);
         checkNode(nodep);
diff --git a/test_regress/t/t_flag_xinitial_unique.v b/test_regress/t/t_flag_xinitial_unique.v
index 04321788a..aff70e92c 100644
--- a/test_regress/t/t_flag_xinitial_unique.v
+++ b/test_regress/t/t_flag_xinitial_unique.v
@@ -6,10 +6,13 @@
 
 module t (/*AUTOARG*/
    // Outputs
-   value
+   value, value2
    );
 
    output reg [63:0] value;
+   output wire [64:0] value2;
+
+   assign value2 = {8'bx, 57'h12};
 
    initial begin
       $write("*-* All Finished *-*\n");