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Fix parameter pins interspersed with cells broke in 3.840.

This commit is contained in:
Wilson Snyder 2012-09-07 19:51:41 -04:00
parent 3d9540c58c
commit c378d32c85
4 changed files with 54 additions and 0 deletions
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5
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@ -3,6 +3,11 @@ Revision history for Verilator
The contributors that suggested a given feature are shown in []. [by ...]
indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.84** devel
**** Fix parameter pins interspersed with cells broke in 3.840. [Bernard Deadman]
* Verilator 3.841 2012/09/03
*** Add --savable to support model save/restore. [Jeremy Bennett]

3
src/V3LinkDot.cpp
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@ -154,6 +154,7 @@ public:
// See t_gen_forif.v for an example.
} else {
preErrorDump();
UINFO(4,"name "<<name<<endl); // Not always same as nodep->name
UINFO(4,"Var1 "<<nodep<<endl);
UINFO(4,"Var2 "<<fnodep<<endl);
if (nodep->type() == fnodep->type()) {
@ -497,6 +498,7 @@ private:
AstBegin* oldbeginp = m_beginp;
VSymEnt* oldModSymp = m_modSymp;
VSymEnt* oldCurSymp = m_curSymp;
int oldParamNum = m_paramNum;
// Where do we add it?
VSymEnt* aboveSymp = m_curSymp;
string origname = AstNode::dedotName(nodep->name());
@ -522,6 +524,7 @@ private:
m_beginp = oldbeginp;
m_modSymp = oldModSymp;
m_curSymp = oldCurSymp;
m_paramNum = oldParamNum;
}
virtual void visit(AstCellInline* nodep, AstNUser*) {
UINFO(5," CELLINLINE under "<<m_scope<<" is "<<nodep<<endl);

14
test_regress/t/t_inst_prepost.pl Executable file
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@ -0,0 +1,14 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
ok(1);
1;

32
test_regress/t/t_inst_prepost.v Normal file
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@ -0,0 +1,32 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t;
sub #(10,11,12,13) sub ();
endmodule
module sub ();
parameter A = 0;
parameter B = 1;
ip ip();
parameter C = 2;
parameter D = 3;
initial begin
if (A!=10) $stop;
if (B!=11) $stop;
if (C!=12) $stop;
if (D!=13) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module ip;
endmodule